Thursday, October 10 • Santa Clara, CA

Thursday, October 17 • Hsinchu, Taiwan

8:30-9:30AMOnsite check-in for registered attendees

Welcome & Opening Remarks

Jonathan Hinkle, Lenovo/Program Chair


Overview of System & App Requirements Influencing NVDIMM-P Definition

Presenter: Aaron Nygren, AMD

This session will give an overview of the system requirements that have influenced the NVDIMM-P definition. Topics covered will include heterogeneous DDR channels and physical constraints, capacity economics, sensible latency, asynchronous non-deterministic responses vs deterministic, and last but not least system RAS.


NVDIMM-P Introduction, Overview and Methodology

Presenter: Wendy Elsasser, ARM

This presentation will introduce the audience to the NVDIMM-P protocol, illustrating how the DRAM bus is re-used as well as the changes made to incorporate support of non-volatile media. This includes support for a larger address space, non-deterministic responses, RAS capabilities, additional meta-data, and flow control. The need for persistence and mechanisms incorporated to ensure data integrity across power fail events will also be highlighted.


NVDIMM-P Power-on, Initialization and Training, Registers, SPD

Presenter: Tsun Ho Liu, Synopsys

This session will cover NVDIMM-P initialization, interface training and registers for DDR4 and DDR5 NVDIMM-P modules. These modules can share the same channel with DDR4 or DDR5 DIMMs and provide additional training features and capability registers. In order to train the media which is controlled by the NVDIMM-P controller, a specific training flow has been defined. Other aspects of the initialization and interface training will cover the response pins, vref and ODT controls, training pattern configuration, optional DQS interval oscillator etc.


NVDIMM-P Write/Read Operations, Utilization 

Presenter: Benjamin Lim, Samsung

XREAD; SREAD; Read ID; LENGTH; tRRSE; maxrdcmdcnt; XWRITE; PWRITE; implicit/explicit flush; FLUSH (push to NVM); flush command modes; ordering rules; WGID bitmap (status/flow); management with no-WGID; Persistence management; energy-backed vs. non Utilization; IOP operation; IOP modes; approval power-down/SREF modes, DFS.


NVDIMM-P Reliability and Optimization Features, MMR and Programming Interface

Presenter: Benjamin Lim, Samsung

UNMAP, Sanitization, Other commands (MPC, etc.), Error Handling, MMR, Highlight aspects of other specs (DDR, BAEBI) that have been leveraged.


DDR5 NVDIMM-P Specifics Preview

Presenter: Frank Ross, Micron Technology (CA only; Taiwan presenter TBD)

Overview and explanation of the coming DDR5 NVDIMM-P specification and the expanded features supported in that standard for modules compatible in the channel with DDR5 DIMMs.


DDR5 NVDIMM-P Profiles Overview (Expected Module Types, etc.)

Presenter: Frank Ross, Micron Technology (CA only; Taiwan presenter TBD)

Introduction to the NVDIMM-P profiles methodology for definition of the common supported features for different implementations of NVDIMM-P.


Wrap Up

Presenter: Frank Ross, Micron Technology (CA only; Taiwan presenter TBD)

Program, topics and speakers subject to change without notice.