Global Standards for the Microelectronics Industry
Tutorial on Memory Modules, Configurations & a New SPD Architecture Using MIPI I3C
Wednesday, March 28, 2018 • Santa Clara, CA
Principal Systems Architect, Nantero
Vice-Chairman, JEDEC JC-45 Committee for DRAM Modules
Chairman, SPD & System Management Bus Task Group
Chairman, MIPI-JEDEC I3C Liaison Sub-Group
Director of New Concept & Product Strategy for Memory Interface Products, IDT
|8:30AM||Registered attendee check-in & continental breakfast|
Why You Should Attend
This training session describes the variety of market-specific memory modules in development in the industry and coordinated through JEDEC. Some are refreshes of previous generations, such as SO-DIMMs for notebook computers and RDIMMs for cloud servers. Others are radically new architectures such as NVDIMM-P for meeting the needs of a growing heterogeneous memory hierarchy.
New on many DDR5 module configurations is on-module power management, with a new standard PMIC for high-density memories. Also introduced in the DDR5 generation is a new system management bus to replace the I2C bus used in all previous generations of SDRAM products. JEDEC and the MIPI Alliance are currently collaborating on the development of a low voltage, high-performance implementation of MIPI I3C with a hub architecture, in-band interrupts, and control of the new PMICs.
Who Should Attend
Application and R&D engineers in computing, storage, consumer electronics, telecom, networking and other areas involving memory technology.
About Mr. Gervasi
Bill Gervasi has been involved in the definition of Double Data Rate SDRAM and memory modules since their earliest inception. His background is in computer science and career highlights include 19 years at Intel where over the years he was systems hardware designer, software designer, and major accounts manager. Mr. Gervasi subsequently was with S3 as a graphics architecture specialist and at Transmeta as a memory technology analyst. With Netlist, SimpleTech, and US Modular, Mr. Gervasi drove the development of unique memory module configurations. With Nantero, he is developing the application of new non-volatile memories. He has served on the JEDEC Board of Directors and chaired JEDEC committees and task groups through the development of DDR1 through DDR5. Mr. Gervasi holds numerous patents in memory and packaging design, and has performed expert witness testimony in major patent cases.
About Mr. Joehren
Michael Joehren is an active participant in the MIPI I3C SWG and chairing the MIPI-JEDEC I3C liaison sub-group. During his past 23+ years in the semiconductors industry Michael held positions in mixed mode IC design, technical marketing, and system architecture in NXP Semiconductors (formerly Philips Semiconductors) in Germany and the United States. He holds an electrical engineering degree from University of Dortmund, Germany (1993) and is the author/co-author of 15 patents/patent applications.
About Mr. Patel
Sam Patel is a Director of New Concept & Product Strategy for Memory Interface Products at IDT. Sam is with IDT for more than 2 years. Prior to IDT, Sam was a Principal Member of Technical Staff focusing on development of Memory Sub-System for Server and various types of Client Systems. Sam was with AMD for more than 14 years. Prior to that, Sam was at IBM for over 4 years. Sam has Bachelor’s and Master’s Degree in Electrical Engineering.