JEDEC LPDDR5 Workshop

Monday, October 7 • Santa Clara, CA


Monday, October 14 • Hsinchu, Taiwan

8:30-9:30AMOnsite check-in for registered attendees
9:30-9:35AM

Welcome Remarks

Hung Vuong, JC-42.6 Subcommittee Chair

9:35-10:15AM
 

LPDDR5 System Perspective & Highlights

Presenters: Marc Greenberg and David Pena (California only), Cadence

A system level perspective is presented, highlighting the values LPDDR5 can provide. This session will introduce key new technology (architecture, interface, addressing, functions and features, packages, modules) and will highlight key differences from LPDDR4. This presentation sets the stage for the subsequent detailed/educational presentations.

10:15-11:15AM
 

LPDDR5 Overview & Operation

Presenter: Osamu Nagashima, Micron Technology

This session will review the key changes from LPDDR4 to LPDDR5 including bank architecture, refresh operations, DCA, DCM and pin configuration. Latency variation/impact due to the changes will also be discussed.

11:15AM-Noon
 

LPDDR5 Clocking and Read/Write Operation

Presenters: YeonKyu Choi (Taiwan) and Dokyun Kim (California), Samsung

LPDDR5 clocking architecture has been updated to run at higher data rate. This session will review the clock architecture mode of operations, syncing, read/write operations, and the LPDDR5 interface. Power supplies will also be addressed, including DVFS, power saving mode, and power-down & Deep Sleep mode of operation.

Noon-1:00PMLunch
1:00-1:45PM
 

LPDDR5 SPEC3

Presenter: Alex Chang (California) and Jeff Choi (Taiwan), SK Hynix

More details coming soon.

1:45-2:30PM

LPDDR5 System Training

Presenters: Tsun Ho Liu (Taiwan), Rajesh Mahajan and Brett Murdock (California), Synopsys

Training and calibration sequences will be reviewed, highlighting new sequences and the differences between LPDDR4 and LPDDR5.

2:30-3:30PM

LPDDR5 Techniques for Validation and Debugging

Presenters: Barbara Aichinger, FuturePlus and Perry Keller, Keysight

This presentation is intended to address the interface from a test/validation aspect, rather than from a design standpoint – addressing the challenges in verifying and validating the interfaces.

3:30-4:00PM

Wrap-up

Presenter: Osamu Nagashima, Micron Technology

This presentation will review the material covered during the workshop, highlighting the key aspects of LPDDR5, including new functions, features, key challenges and validation/characterization aspects.

4:00-4:30PM

Panel Discussion

Program, topics and speakers subject to change without notice.