Global Standards for the Microelectronics Industry
Standards & Documents Search
| Title | Document # |
Date |
|---|---|---|
DDR5 Load Reduced (LRDIMM) and Registered Dual Inline Memory Module (RDIMM) Common Specification |
JESD305 | Jan 2022 |
This standard defines the electrical and mechanical requirements for 288-pin, 1.1 Volt (VDD and VDDQ), DDR5 Registered (RDIMM) and Load Reduced (LRDIMM), Double Data Rate (DDR), Synchronous DRAM Dual In-Line Memory Modules (DIMM). These 288-pin Registered and Load Reduced DDR5 SDRAM DIMMs are intended for use in server, workstation, and database environments. Item 2273.07. Committee(s): JC-45.1 Free download. Registration or login required. |
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TEST METHOD FOR THE MEASUREMENT OF MOISTURE DIFFUSIVITY AND WATER SOLUBILITY IN ORGANIC MATERIALS USED IN ELECTRONIC DEVICES |
JESD22-A120C | Jan 2022 |
This standard details the procedures for the measurement of characteristic bulk material properties of moisture diffusivity and water solubility in organic materials used in the packaging of electronic devices. These two material properties are important parameters for the effective reliability performance of plastic packaged surface mount devices after exposure to moisture and subjected to high temperature solder reflow. Committee(s): JC-14.1 Free download. Registration or login required. |
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High Bandwidth Memory DRAM (HBM3) |
JESD238 | Jan 2022 |
The HBM3 DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM3 DRAM uses a wide-interface architecture to achieve high-speed, low power operation. Each channel interface maintains a 64 bit data bus operating at double data rate (DDR). Item 1837.98. Committee(s): JC-42.2 Free download. Registration or login required. |
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TS5111, TS5110 Serial Bus Thermal Sensor Device Standard |
JESD302-1 | Jan 2022 |
This standard defines the specifications of interface parameters, signaling protocols, and features for fifth generation Temperature Sensor (TS5) as used for memory module applications. These device operate on I2C and I3C two-wire serial bus interface. The designation TS5111 and TS5110 refers to the device specified by this document. Item 401.01E Committee(s): JC-40.1 Free download. Registration or login required. |
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STANDARD MANUFACTURERS IDENTIFICATION CODENOTE: JEP106U was in error starting with bank two an additional continuation code was added, JEP106U should be discarded. |
JEP106BE | Jan 2022 |
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to http://www.jedec.org/Home/MIDCODE_request.cfm Free download. Registration or login required. |
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Registration - Enclosure Form Factor for Automotive SSD Connector, Cable Mount |
SO-029A | Jan 2022 |
Designator: PBXC-K4_D#p##-MR36p05x14p5Z10p25-HS Cross Reference: MO-348 Committee(s): JC-11.14 Free download. Registration or login required. |
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IC LATCH-UP TEST |
JESD78F | Jan 2022 |
This standard covers the I-test and Vsupply overvoltage latch-up testing of integrated circuits. The purpose of this standard is to establish a method for determining IC latch-up characteristics and to define latch-up detection criteria. Latch-up characteristics are extremely important in determining product reliability and minimizing No Trouble Found (NTF) and Electrical Overstress (EOS) failures due to latch-up. This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies. This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880. Committee(s): JC-14.1 Free download. Registration or login required. |
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Test Procedure for the Measurement of Terrestrial Cosmic Ray Induced Destructive Effects in Power Semiconductor Devices |
JEP151A | Jan 2022 |
This test method defines the requirements and procedures for terrestrial destructive* single-event effects (SEE) for example, single-event breakdown (SEB), single-event latch-up (SEL) and single-event gate rupture (SEGR) testing . It is valid when using an accelerator, generating a nucleon beam of either; 1) Mono-energetic protons or mono-energetic neutrons of at least 150 MeV energy, or 2) Neutrons from a spallation spectrum with maximum energy of at least 150 MeV. This test method does not apply to testing that uses beams with particles heavier than protons. *This test method addresses a separate risk than does JESD89 tests for non-destructive SEE due to cosmic radiation effects on terrestrial applications.
Committee(s): JC-14.1 Free download. Registration or login required. |
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SERIAL INTERFACE FOR DATA CONVERTERS |
JESD204C.01 | Jan 2022 |
This is a minor editorial change to JESD204C, the details can be found in Annex A. This standard describes a serialized interface between data converters and logic devices. It contains normative information to enable designers to implement devices that communicate with other devices covered by this document. Informative sections are included to clarify and exemplify the standard. Item 192.02B. Committee(s): JC-16 Free download. Registration or login required. |
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DDR5 Buffer Definition (DDR5DB01) - Rev. 1.1 |
JESD82-521 | Dec 2021 |
This standard defines standard specifications for features and functionality, DC & AC interface parameters and test loading for definition of the DDR5 data buffer for driving DQ and DQS nets on DDR5 LRDIMM applications. The purpose is to provide a standard for the DDR5DB01 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Item 323.98K Committee(s): JC-40.4 Free download. Registration or login required. |
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Backup Energy Module Standard for NVDIMM Memory Devices (BEM) |
JESD315 | Dec 2021 |
This standard defines the functional requirements of Backup Energy Module (BEM), henceforth referred to as BEM in this standard. This module shall be used to provide backup power to the Industry Defined Storage Array Controller Cards and NVDIMM-n as applicable. All standards are applicable under all operating conditions unless otherwise stated. Item 2279.03 Committee(s): JC-45 Free download. Registration or login required. |
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Guidelines for Representing Switching Losses of SIC MOSFETs in Datasheets |
JEP187 | Dec 2021 |
This document describes the impact of measurement and/or setup parameters on switching losses of power semiconductor switches; focusing primarily on SiC MOSFET turn-on losses. In terms of turn-off losses, the behavior of SiC MOSFETs is similar to that of existing silicon based power MOSFETs, and as such are adequately represented in typical datasheets. Committee(s): JC-70.2 Free download. Registration or login required. |
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Guideline to Specify a Transient Off-State Withstand Voltage Robustness Indicator in Datasheets for Lateral GaN Power Conversion Devices, Version 1.0 |
JEP186 | Dec 2021 |
This guideline describes different techniques for specifying a Transient Off-state Withstand Voltage Robustness Indicator in datasheets for lateral GaN power conversion devices. This guideline does not convey preferences for any of the specification types presented, nor does the guideline address formatting of datasheets. This guideline does not indicate nor require that the datasheet parameters are used in production tests, nor specify how the values were obtained. Committee(s): JC-70.1 Free download. Registration or login required. |
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SERIAL FLASH DISCOVERABLE PARAMETERS (SFDP) |
JESD216F | Dec 2021 |
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. Any company may request a Function Specific ID by making a request to the JEDEC office at juliec@jedec.org. Please include “Function Specific ID Request, JESD216” in the email subject line. Item 1775.73. Committee(s): JC-42.4 Free download. Registration or login required. |
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JEDEC MODULE SIDEBAND BUS (SidebandBus) |
JESD403-1A | Dec 2021 |
This standard defines the assumptions for the system management bus for next generation memory solutions; covering the interface protocol, use of hub devices, and voltages appropriate to these usages. Item 2260.56. Committee(s): JC-45 Free download. Registration or login required. |
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Registration - Plastic Bottom Grid Array Ball, 0.35 mm x 0.40 mm Pitch Rectangular Family Package |
MO-350A | Nov 2021 |
Designator: PBGA-B#[#]_I0p35...Item 11-998 Committee(s): JC-11.11 Free download. Registration or login required. |
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Registration - Silicon Bottom Grid Array Column, 0.048 mm x 0.055 mm Pitch Square Package |
MO-349A | Nov 2021 |
Designator: SBGA-M7775[23828]_D0p073... Item: 11.4-996 Access STP Files for MO-349ACross Reference: DR4.26 Committee(s): JC-11.4 Free download. Registration or login required. |
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SEMICONDUCTOR WAFER AND DIE BACKSIDE EXTERNAL VISUAL INSPECTION |
JESD22-B118A | Nov 2021 |
This inspection method is for product semiconductor wafers and dice prior to assembly. This test method defines the requirements to execute a standardized external visual inspection and is a non-invasive and nondestructive examination that can be used for qualification, quality monitoring, and lot acceptance. Committee(s): JC-14.1 Free download. Registration or login required. |
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DEFINITION OF THE SSTUA32S865 AND SSTUA32D865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS |
JESD82-19A.01 | Oct 2021 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUA32S865 and SSTUA32D865 registered buffer with parity for 2 rank by 4 or similar high-density DDR2 RDIMM applications. This is a minor editor revision as shown in Annex A of the document. Committee(s): JC-40 Free download. Registration or login required. |
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DEFINITION OF THE SSTU32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS |
JESD82-10A.01 | Oct 2021 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTU32866 registered buffer with parity test for DDR2 RDIMM applications. The purpose is to provide a standard for the SSTU32866 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor editorial revision as shown in Annex A of the document. Free download. Registration or login required. |
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NAND FLASH INTERFACE INTEROPERABILITY |
JESD230E | Oct 2021 |
This document defines a standard NAND flash device interface interoperability standard that provides means for a system to be designed that can support Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices that are interoperable between JEDEC and ONFI member implementations. This standard was jointly developed by JEDEC and the Open NAND Flash Interface Workgroup, hereafter referred to as ONFI. Item 1767.57 Committee(s): JC-42.4 Free download. Registration or login required. |
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Registration - Shipping and Handling Tray for DDR5 DIMM Microelectronic Assembly |
CO-036B | Oct 2021 |
Designator: N/A Committee(s): JC-11.5 Free download. Registration or login required. |
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REGISTRATION - Battery Cell R/A SMT Type Connector, 1.2 mm Pitch |
SO-028A | Oct 2021 |
Designator: PSXC-L6_I1p2-R11p6x5p85Z2p07-R0p3x0p6ET0p07 Committee(s): JC-11.14 Free download. Registration or login required. |
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REGISTRATION - Battery Cell R/A T/H Type Connector, 1.2 mm Pitch |
SO-026A | Oct 2021 |
Designator: PSXC-P6_I1p2-R11p6x5p85Z2p0-R0p3x0p31H1p16 Committee(s): JC-11.14 Free download. Registration or login required. |
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DDR5 SDRAM |
JESD79-5A | Oct 2021 |
This document defines the DDR5 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 8Gb through 32Gb for x4, x8, and x16 DDR5 SDRAM devices. This standard was created based on the DDR4 standards (JESD79-4) and some aspects of the DDR, DDR2, DDR3 & LPDDR4 standards (JESD79, JESD79-2, JESD79-3 & JESD209-4). Item 1848.99K. Committee(s): JC-42.3B Available for purchase: $369.00 Add to Cart Paying JEDEC Members may login for free access. |
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DEFINITION OF SSTU32865 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS |
JESD82-9B.01 | Oct 2021 |
This standard provides the functional definition, ball-out configuration and package outline, signal definitions and input/output characteristics for a 28-bit 1:2 registered driver with parity suitable for use on DDR2 RDIMMs. The SSTU32865 integrates the functional equivalent of two SSTU32864 devices (as defined in JESD82-7) into a single device, thereby easing layout and board design constraints especially on high density RDIMMs such as dual rank, by four configurations. Moreover, the optional use of a parity function is provided for, permitting detection and reporting of parity errors across its 22 data inputs. JESD82-9 specifies a 160-pin Thin-profile, fine-pitch ball-grid array (TFBGA) package. This is a minor editorial revision as shown in Annex A of the document. Free download. Registration or login required. |
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STANDARD FOR DEFINITION OF THE SSTV16859 2.5 V, 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR STACKED DDR DIMM APPLICATIONS: |
JESD82-4B.01 | Oct 2021 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV16859 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM applications. The purpose is to provide a standard for the SSTV16859 logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor editorial revision, shown in Annex A of the document. Committee(s): JC-40 Free download. Registration or login required. |
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DEFINITION OF THE SSTUA32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY TEST FOR DDR2 RDIMM APPLICATIONS |
JESD82-16A.01 | Oct 2021 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUA32866 registered buffer with parity test for DDR2 RDIMM applications. The purpose is to provide a standard for the SSTUA32866 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor editorial revision as shown in Annex A of the document. Free download. Registration or login required. |
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DEFINITION OF THE SSTUB32868 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS |
JESD82-14A.01 | Oct 2021 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32868 registered buffer with parity test for DDR2 RDIMM applications. SSTU32S2868 denotes a single-die implementation and SSTU32D868 denotes a dual-die implementation. This is a minor editorial revision as shown in Annex A of the document. Committee(s): JC-40 Free download. Registration or login required. |
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Registration - Battery Cell Wire Side Connector, 1.2 mm pitch |
SO-027A | Sep 2021 |
Designator: PBXC-q6_i1P2-r7P9X4P25z1P58Item: 11.14-199, Access STP Files for SO-027ACross Reference: N/A Committee(s): JC-11.14 Free download. Registration or login required. |
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TEST METHOD FOR BEAM ACCELERATED SOFT ERROR RATE |
JESD89-3B | Sep 2021 |
This test is used to determine the terrestrial cosmic ray Soft Error Rate (SER) sensitivity of solid state volatile memory arrays and bistable logic elements (e.g., flip-flops) by measuring the error rate while the device is irradiated in a neutron or proton beam of known flux. The results of this accelerated test can be used to estimate the terrestrial cosmic ray induced SER for a given terrestrial cosmic ray radiation environment. This test cannot be used to project alpha-particle induced SER. Committee(s): JC-14.1 Free download. Registration or login required. |
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Addendum No. 1 to JESD251 - OPTIONAL x4 QUAD I/O WITH DATA STROBE |
JESD251-1.01 | Sep 2021 |
This purpose of the addendum is to add an optional 4-bit bus width (x4) to JESD251, xSPI standard. The xSPI interface currently supports a x1 interface that acts as a bridge to legacy SPI functionality as well as the x8 interface intended to achieve dramatically higher bus performance than legacy SPI memory implementations. Item 1775.15. This is an editorial revision to JESD251-1, October 2018 Committee(s): JC-42.4 Free download. Registration or login required. |
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MEASUREMENT AND REPORTING OF ALPHA PARTICLE AND TERRESTRIAL COSMIC RAY INDUCED SOFT ERRORS IN SEMICONDUCTOR DEVICES |
JESD89B | Sep 2021 |
This specification defines the standard requirements and procedures for terrestrial soft-error-rate (SER) testing of integrated circuits and reporting of results. Both real-time (unaccelerated) and accelerated testing procedures are described. At terrestrial, Earth-based altitudes, the predominant sources of radiation include both cosmic-ray radiation and alpha-particle radiation from radioisotopic impurities in the package and chip materials. An overall assessment of a deviceís SER is complete, only when an unaccelerated test is done, or accelerated SER data for the alpha-particle component and the cosmic-radiation component has been obtained. Free download. Registration or login required. |
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Registration - Plastic, Ultra, Extra and Super Thin, Fine Pitch, Dual Small Outline, Flat, Leaded Package. (U, X1, X2)F-PSOF, HX2-PSOF. |
MO-293B | Sep 2021 |
Item 11.10-459 Committee(s): JC-11.10 Free download. Registration or login required. |
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Registration - 288 Pin DDR5 DIMM, 0.85 mm Pitch Microelectronic Assembly |
MO-329D | Sep 2021 |
Designator: PDMA-N288-I0p85-R133p8x#p#7Z31p8R2p55x0p6 Patents(): Micron: US7,547,213. Committee(s): JC-11.14 Free download. Registration or login required. |
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EXPANDED SERIAL PERIPHERAL INTERFACE (xSPI) FOR NON VOLATILE MEMORY DEVICES |
JESD251B | Sep 2021 |
This standard is intended for use by SoC, ASIC, ASSP, and FPGA developers or vendors interested in incorporating a master interface having a low signal count and high data transfer bandwidth with access to multiple sources of slave devices compliant with the interface. It is also, intended for use by peripheral developers or vendors interested in providing slave devices compliant with the standard, including non-volatile memories, volatile memories, graphics peripherals, networking peripherals, FPGAs, sensors, etc. Item 1775.64. Committee(s): JC-42.4 Free download. Registration or login required. |
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DDR5 REGISTERING CLOCK DRIVER DEFINITION (DDR5RCD01) |
JESD82-511 | Aug 2021 |
This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM and LRDIMM applications. The DDR5RCD01 Device ID is DID = 0x0051. Committee(s): JC-40.4 Free download. Registration or login required. |
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DDR5 288 Pin U/R/LR DIMM Connector Performance Standard, DDR5 |
PS-005A.01 | Aug 2021 |
Committee(s): JC-11.14 Free download. Registration or login required. |
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ENCLOSURE FORM FACTOR FOR SSD DEVICES, VERSION 1.0 |
JESD253.01 | Aug 2021 |
This document specifies the enclosure form factor which can be used with various type of SSD devices: outline of the top and bottom enclosure, three screw holes to mount the enclosure on the system, and two clamping holes in the top enclosure to lock to the connector. Item 318.06. This is a minor editorial revision detailed in Annex D. Committee(s): JC-64.8 Free download. Registration or login required. |
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GENERAL REQUIREMENTS FOR DISTRIBUTORS OF COMMERCIAL AND MILITARY SEMICONDUCTOR DEVICES |
JESD31F | Aug 2021 |
This standard identifies the general requirements for Distributors that supply Commercial and Military products. This standard applies to all discrete semiconductors, integrated circuits and Hybrids, whether packaged or in wafer/die form, manufactured by all Manufacturers. The requirements defined within this document are only applicable to products for which ownership remains with the Distributor or Manufacturer. Free download. Registration or login required. |
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XFM DEVICE, Version 1.0 |
JESD233 | Aug 2021 |
This standard specifies the mechanical and electrical characteristics of the XFM Device. Such characteristics include, among others, package dimensions, pin layout, signal assignment, power supply voltages, currents, and electrical characteristics of the PCIe interface. Committee(s): JC-64 Free download. Registration or login required. |
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COPY-EXACT PROCESS FOR MANUFACTURING |
JEP185 | Aug 2021 |
This publication defines the requirements for Copy-Exact Process (CEP) matching, real-time process control, monitoring, and ongoing assessment of the CEP. The critical element requirements for inputs, process controls, procedures, process indicators, human factors, equipment/infrastructure and matching outputs are given. Manufacturers, suppliers and their customers may use these methods to define requirements for process transfer within the constraints of their business agreements. Committee(s): JC-14.3 Free download. Registration or login required. |
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PMIC50x0 POWER MANAGEMENT IC SPECIFICATION, Rev. 1.8 |
JESD301-1A | Aug 2021 |
Definition of PMIC5000, PMIC5010 Voltage Regulator Device for Memory Module Applications. Item 325.29C Committee(s): JC-40.1 Free download. Registration or login required. |
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TEST METHOD FOR REAL-TIME SOFT ERROR RATE |
JESD89-1B | Jul 2021 |
This test is used to determine the Soft Error Rate (SER) of solid state volatile memory arrays and bistable logic elements (e.g. flip-flops) for errors which require no more than re-reading or re-writing to correct and as used in terrestrial environments. It simulates the operating condition of the device and is used for qualification, characterization, or reliability monitoring. This test is intended for execution in ambient conditions without the artificial introduction of radiation sources. Free download. Registration or login required. |
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TEST METHOD FOR ALPHA SOURCE ACCELERATED SOFT ERROR RATE |
JESD89-2B | Jul 2021 |
This test method is offered as standardized procedure to determine the alpha particle Soft Error Rate (SER) sensitivity of solid state volatile memory arrays and bistable logic elements (e.g. flipflops) by measuring the error rate while the device is irradiated by a characterized, solid alph source. Free download. Registration or login required. |
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HIGH TEMPERATURE STORAGE LIFE |
JESD22-A103E.01 | Jul 2021 |
The test is applicable for evaluation, screening, monitoring, and/or qualification of all solid state devices. The high temperature storage test is typically used to determine the effects of time and temperature, under storage conditions, for thermally activated failure mechanisms and time-to failure distributions of solid state electronic devices, including nonvolatile memory devices (data retention failure mechanisms). Thermally activated failure mechanisms are modeled using the Arrhenius Equation for acceleration. During the test, accelerated stress temperatures are used without electrical conditions applied. This test may be destructive, depending on time, temperature and packaging (if any). Committee(s): JC-14.1 Available for purchase: $55.00 Add to Cart Paying JEDEC Members may login for free access. |
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METHODS FOR CALCULATING FAILURE RATES IN UNITS OF FITS |
JESD85A | Jul 2021 |
This standard establishes methods for calculating failure rates in units of FITs by using data in varying degrees of detail such that results can be obtained from almost any data set. The objective is to provide a reference to the way failure rates are calculated. Committee(s): JC-14.3 Free download. Registration or login required. |
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Registration - Plastic Dual Small Outline Surface Terminal, Wettable Flank Package |
MO-340B | Jul 2021 |
Designator: PDSO_N#[#]_I#-R#x#Z#-CturET0p04 Patents(): Nexperia BV: 8809121B2 Committee(s): JC-11.11 Free download. Registration or login required. |
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DDR4 SDRAM STANDARD |
JESD79-4D | Jul 2021 |
This document defines the DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 2 Gb through 16 Gb for x4, x8, and x16 DDR4 SDRAM devices. This standard was created based on the DDR3 standard (JESD79-3) and some aspects of the DDR and DDR2 standards (JESD79, JESD79-2). Committee Item 1716.78H Committee(s): JC-42.3C Available for purchase: $284.00 Add to Cart Paying JEDEC Members may login for free access. |
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Registration - Metal Enclosure for SSD Devices, E1.S and M.2 |
MO-348A | Jul 2021 |
Designator: MMXH-R(##)x36p75Z(##) Committee(s): JC-11.14 Free download. Registration or login required. |
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LOW POWER DOUBLE DATA RATE 5 (LPDDR5) |
JESD209-5B | Jun 2021 |
This document defines the LPDDR5 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant x16 one channel SDRAM device and x8 one channel SDRAM device. LPDDR5 device density ranges from 2 Gb through 32 Gb. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3) and LPDDR4 (JESD209-4). Item 1854.99B. Available for purchase: $400.00 Add to Cart Paying JEDEC Members may login for free access. |
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LOW POWER DOUBLE DATA RATE 4 (LPDDR4) |
JESD209-4D | Jun 2021 |
This document defines the LPDDR4 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this standard is to define the minimum set of requirements for a JEDEC compliant 16 bit per channel SDRAM device with either one or two channels. LPDDR4 dual channel device density ranges from 4 Gb through 32 Gb and single channel density ranges from 2 Gb through 16 Gb. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209), LPDDR2 (JESD209-2) and LPDDR3 (JESD209-3). Committee Item: 1824.42D Committee(s): JC-42.6 Available for purchase: $327.00 Add to Cart Paying JEDEC Members may login for free access. |
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184 Pin, PC-1600/PC-2100 DDR SDRAM Unbuffered DIMM Design Specification. |
MODULE4.20.5 | May 2021 |
Release No. 31This revision contains terminology updates only. JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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184-Pin PC-2700 SDRAM Unbuffered DIMM - TSOP-Based DRAMs Design Specification |
MODULE4.20.8 | May 2021 |
Release No. 31This revision contains terminology updates only. JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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PC-1600/PC-2100 DDR SDRAM Registered DIMM Design Specification (184 Pin) |
MODULE4.20.4 | May 2021 |
Release No. 31This revision contains terminology updates only. Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Unbuffered DIMM Design Specification |
MODULE4.20.19 | May 2021 |
Release No. 31. Item 2131.03, 2078.04, 2131.06This revision contains terminology updates only. Committee(s): JC-45, JC-45.2, JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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240-Pin Unbuffered and Registered DDR2 SDRAM DIMM Family |
MODULE4.5.14 | May 2021 |
Release No. 31This revision contains terminology updates only. JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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184 Pin Unbuffered SDR SDRAM DIMM Family |
MODULE4.5.11 | May 2021 |
Release No.31This revision contains terminology updates only. Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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184 Pin Unbuffered DDR SDRAM DIMM |
MODULE4.5.10 | May 2021 |
Release No.31This revision contains terminology updates only. JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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240-Pin PC2-5300/PC2-6400 DDR2 SDRAM Unbuffered DIMM Design Specification |
MODULE4.20.13 | May 2021 |
Release 31. Item 2167.05This revision contains terminology updates only. Committee(s): JC-45, JC-45.2, JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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