Global Standards for the Microelectronics Industry
Standards & Documents Search
Title | Document # |
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Universal Flash Storage Host Controller Interface (UFSHCI), Version 4.0 |
JESD223E | Aug 2022 |
This standard describes a functional specification of the Host Controller Interface (HCI) for Universal Flash Storage (UFS). The objective of UFSHCI is to provide a uniform interface method of accessing the UFS hardware capabilities so that a standard/common Driver can be provided for the Host Controller. The common Driver would work with UFS host controller from any vendor. This standard includes a description of the hardware/software interface between system software and the host controller hardware. It is intended for hardware designers, system builders and software developers. This standard is a companion document to [UFS], Universal Flash Storage (UFS). The reader is assumed to be familiar with [UFS], [MIPI-UNIPRO], and [MIPI-M-PHY]. Item 206.25 Committee(s): JC-64.1 Free download. Registration or login required. |
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UNIVERSAL FLASH STORAGE, Version 4.0 |
JESD220F | Aug 2022 |
This document replaces all past versions, however JESD220E, January 2020 (V 3.1), is available for reference only. This standard specifies the characteristics of the UFS electrical interface and the memory device. Such characteristics include (among others) low power consumption, high data throughput, low electromagnetic interference and optimization for mass memory subsystem efficiency. The UFS electrical interface is based on an advanced differential interface by MIPI M-PHY specification which together with the MIPI UniPro specification forms the interconnect of the UFS interface. Committee(s): JC-64.1 Available for purchase: $369.00 Add to Cart Paying JEDEC Members may login for free access. |
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LONG-TERM STORAGE GUIDELINES FOR ELECTRONIC SOLID-STATE WAFERS, DICE, AND DEVICES |
JEP160A | Aug 2022 |
This publication examines the LTS requirements of wafers, dice, and packaged solid-state devices. The user should evaluate and choose the best practices to ensure their product will maintain as-received device integrity and minimize age- and storage-related degradation effects. Free download. Registration or login required. |
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DDR5 UDIMM Raw Card Annex BRelease Number: Version 1.0 |
JESD308-U0-RCB | Jul 2022 |
This annex JESD308-U0-RCB, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Raw Card B Annex defines the design detail of x8, 2 Package Ranks DDR5 UDIMM. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard. Item 2265.11A Committee(s): JC-45.3 Free download. Registration or login required. |
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DDR5 UDIMM Raw Card Annex ERelease Number: Version 1.0 |
JESD308-U4-RCE | Jul 2022 |
This annex JESD308-U4-RCE, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) with 4-bit ECC (EC4 SODIMM) Raw Card E Annex" defines the design detail of x8, 2 Package Ranks DDR5 ECC UDIMM. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard. Item 2265.12A Committee(s): JC-45.3 Free download. Registration or login required. |
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DDR5 UDIMM Raw Card Annex ARelease Number: Version 1.0 |
JESD308-U0-RCA | Jul 2022 |
This annex JESD308-U0-RCA, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Raw Card AAnnex defines the design detail of x8, 1 Package Rank DDR5 UDIMM. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard. Item 2265.13A Committee(s): JC-45.3 Free download. Registration or login required. |
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DDR5 UDIMM Raw Card Annex ARelease Number: Version 1.0 |
JESD308-U0-RCA | Jul 2022 |
This annex JESD308-U0-RCA, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Raw Card AAnnex defines the design detail of x8, 1 Package Rank DDR5 UDIMM. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard. Item 2265.13A Committee(s): JC-45.3 Free download. Registration or login required. |
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DDR5 UDIMM Raw Card Annex DRelease Number: Version 1.0 |
JESD308-U4-RCD | Jul 2022 |
This annex JESD308-U4-RCD, DDR5 Unbuffered Dual Inline Memory Module with 4-bit ECC (EC4UDIMM) Raw Card D Annex defines the design detail of x8, 1 Package Rank DDR5 UDIMM with 4-bit ECC. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard. Item 2265.14A Free download. Registration or login required. |
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DDR5 UDIMM Raw Card Annex CRelease Number: Version 1.0 |
JESD308-U0-RCC | Jul 2022 |
This annex JESD308-U0-RCC, “DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Raw Card C Annex” defines the design detail of x16, 1 Package Ranks DDR5 UDIMM. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard. Item 2265.08A Committee(s): JC-45.3 Free download. Registration or login required. |
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SPD5118 HUB AND SERIAL PRESENCE DETECT DEVICE STANDARDRelease Number: Version 1.5 |
JESD300-5B | Jul 2022 |
This standard defines the specifications of interface parameters, signaling protocols, and features for DDR5 Serial Presence Detect EEPROM with Hub function (SPD5 Hub) and integrated Temperature Sensor (TS) as used for memory module applications. The Hub feature allows isolation of a local bus from a Controller host bus. The designation SPD5118 or generic term SPD5 Hub refers to the devices specified by this standard. Committee Item 600.02A Committee(s): JC-40.1 Free download. Registration or login required. |
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Registration - Plastic Dual Small Outline, 1.00 MM pitch5.48 MM width Rectangular Family Package |
MO-351A | Jun 2022 |
PDSO-G10_I1p)...Item 11.11-1005 Committee(s): JC-11.11 Free download. Registration or login required. |
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POD125 - 1.25 V PSEUDO OPEN DRAIN I/O |
JESD8-30A.01 | Jun 2022 |
Editorial Terminology Update. This standard defines the DC and AC single-ended (data) and differential (clock) operating conditions, I/O impedances, and the termination and calibration scheme for 1.25 V Pseudo Open Drain I/Os. The 1.25 V Pseudo Open Drain interface, also known as POD125, is primarily used to communicate with GDDR6 SGRAM devices. Committee(s): JC-16 Free download. Registration or login required. |
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POD135 - 1.35 V PSEUDO OPEN DRAIN I/O |
JESD8-21C.01 | Jun 2022 |
Editorial, Terminology Update. This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedance's, and the termination and calibration scheme for 1.35 V Pseudo Open Drain I/Os. The 1.35 V Pseudo Open Drain interface, also known as POD135, is primarily used to communicate with GDDR5 or GDDR5M SGRAM devices. Item 146.01B Committee(s): JC-16 Free download. Registration or login required. |
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DDR5 Serial Presence Detect (SPD) ContentsRelease Number: Version 1.0 |
JESD400-5 | Jun 2022 |
This document describes the serial presence detect (SPD) values for all DDR5 memory modules. In this context, “modules” applies to memory modules like traditional Dual In-line Memory Modules (DIMMs) or solder-down motherboard applications. The SPD data provides critical information about all modules on the memory channel and is intended to be use by the system's BIOS in order to properly initialize and optimize the system memory channels. Item 2260.01M Committee(s): JC-45 Free download. Registration or login required. |
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SERIAL FLASH DISCOVERABLE PARAMETERS (SFDP)This document replaces JESD216F.01, Editorial changes to this document were approved by the TG, June 2022 |
JESD216F.02 | Jun 2022 |
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. Any company may request a Function Specific ID by making a request to the JEDEC office at juliec@jedec.org. Please include “Function Specific ID Request, JESD216” in the email subject line. Item 1775.73. Editorial changes listed in Annex, from original publication of JESD216F (December 2021). Committee(s): JC-42.4 Free download. Registration or login required. |
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JEDEC COMMITTEE SCOPE MANUAL |
JM18T | Jun 2022 |
The JEDEC Board of Directors is responsible for establishing appropriate committees to conduct its standardization activities. These committees are assigned either service or product responsibilities. It is a primary function of each committee to propose JEDEC Standards and to formulate policies, procedures, formats, and other documents that are then submitted to the Board of Directors for action or approval. This publication identifies the service and product committees established by the Board of Directors and defines their scopes. Committee(s): JC-COUN Free download. Registration or login required. |
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SOLID STATE DRIVE (SSD) REQUIREMENTS AND ENDURANCE TEST METHOD |
JESD218B.02 | Jun 2022 |
Terminology Update, see Annex. This standard defines JEDEC requirements for solid state drives. For each defined class of solid state drive, the standard defines the conditions of use and the corresponding endurance verification requirements. Although endurance is to be rated based upon the standard conditions of use for the class, the standard also sets out requirements for possible additional use conditions as agreed to between manufacturer and purchaser. Revision A includes further information on SSD Capacity. Items 303.19, 303.20, 303.21, 303.22, 303.23, 303.26, 303.27, 303.28, and 303.32 Committee(s): JC-64.8 Available for purchase: $76.00 Add to Cart Paying JEDEC Members may login for free access. |
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JEDEC COMMITTEE SPECIFIC ADDITIONAL POLICIES |
JM12B | Jun 2022 |
In some cases, JEDEC Committees have established additional policies and guidelines to facilitate the operation of a particular committee. Additional policies and guidelines are set forth here as an addendum to JM21 to facilitate the operation of particular committees. These policies are in addition to the requirements set forth in JM21 and in no case shall these additions contradict or supersede the requirements in JM21. Committee(s): JC-JEDC Free download. Registration or login required. |
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SOLID-STATE DRIVE (SSD) ENDURANCE WORKLOADS |
JESD219A.01 | Jun 2022 |
Terminology update, see Annex. This standard defines workloads for the endurance rating and endurance verification of SSD application classes. These workloads shall be used in conjunction with the Solid State Drive (SSD) Requirements and Endurance Test Method standard, JESD218. Also see JESD219A_MT and JESD219A_TT for the supporting trace files. Free download. Registration or login required. |
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DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard |
JESD308 | May 2022 |
This standard defines the electrical and mechanical requirements for 288-pin, 1.1 V (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM UDIMMs). These DDR5 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in Computers. Item 2265.02B Committee(s): JC-45.3 Free download. Registration or login required. |
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DDR5 Small Outline Dual Inline Memory Module (SODIMM) Common Standard |
JESD309 | May 2022 |
This standard defines the electrical and mechanical requirements for 262-pin, 1.1 V (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM SODIMMs). These DDR5 SODIMMs are intended for use as main memory when installed in Computers, laptops and other systems. Item 2262.06B Free download. Registration or login required. |
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EXPANDED SERIAL PERIPHERAL INTERFACE (xSPI) FOR NONVOLATILE MEMORY DEVICES |
JESD251C | May 2022 |
This standard specifies the eXpanded Serial Peripheral Interface (xSPI) for Non Volatile Memory Devices, which provides high data throughput, low signal count, and limited backward compatibility with legacy Serial Peripheral Interface (SPI) devices. It is primarily for use in computing, automotive, Internet Of Things (IOT), embedded systems and mobile systems, between host processing and peripheral devices. The xSPI electrical interface can deliver up to 400 MBytes per second raw data throughput. Item 1775.74. Committee(s): JC-42.4 Free download. Registration or login required. |
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Definition of the EE1002 and EE1002A Serial Presence Detect (SPD) EEPROMs |
SPD4.1.3-01 | May 2022 |
Release No. 19.01. Item 1739.02E, Terminology update. JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Mobile Platform Memory Module Thermal Sensor Component Specification |
MODULE4.7 | May 2022 |
Release No. 16.This replaces Release 15 and includes the following editorial changes: 1) Replaced master/slave with controller/target 2) Checked for presence of other sensitive words 3) Added Tables and Figures in Table of Contents(Release 15, Item 1640.07) Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Definitions of the EE1004-v 4 Kbit Serial Presence Detect (SPD) EEPROM and TSE2004av 4 Kbit SPD EEPROM with Temperature Sensor (TS) for Memory Module Applications |
SPD4.1.6-01 | May 2022 |
Release 26.01, Terminology update This standard defines the specifications of interface parameters, signaling protocols, and features for Serial Presence Detect (SPD) EEPROM (EE) and Temperature Sensor (TS) as used for memory module applications. Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Definition of the TSE2002av Serial Presence Detect (SPD) EEPROM with Temperature Sensor (TS) for Memory Module Applications |
SPD4.1.4-01 | May 2022 |
Release No. 21.01, Terminology update.This standard defines the specifications of interface parameters, signaling protocols, and features for Serial Presence Detect (SPD) EEPROMs and Temperature Sensor (TS) as used for memory module applications. The designation TSE2002av refers to the family of devices specified by this document. Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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DDR5 DIMM Labels |
JESD401-5 | May 2022 |
This standard for labels applies to all DDR5 memory modules to fully describe the key attributes of the module. The label can be in the form of a stick-on label, silk screened onto the assembly, or marked using an alternate customer-readable format, Item 2268.02C Committee(s): JC-45 Free download. Registration or login required. |
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TS5111, TS5110 Serial Bus Thermal Sensor Device Standard |
JESD302-1.01 | Apr 2022 |
This standard defines the specifications of interface parameters, signaling protocols, and features for fifth generation Temperature Sensor (TS5) as used for memory module applications. These device operate on I2C and I3C two-wire serial bus interface. The designation TS5111 and TS5110 refers to the device specified by this document. Item 401.01E. Minor editorial changes listed in Annex A. Committee(s): JC-40.1 Free download. Registration or login required. |
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EXTERNAL VISUAL |
JESD22-B101D | Apr 2022 |
External visual inspection is an examination of the external surfaces, construction, marking, and workmanship of a finished package or component. External visual is a noninvasive and nondestructive test. It is functional for qualification, quality monitoring, and lot acceptance. Committee(s): JC-14.1 Free download. Registration or login required. |
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RECOMMENDED ESD-CDM TARGET LEVELS |
JEP157A | Apr 2022 |
This document was written with the intent to provide information for quality organizations in both semiconductor companies and their customers to assess and make decisions on safe ESD CDM level requirements. Free download. Registration or login required. |
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DDR5 RDIMM Standard Annex ERelease Number: Version 1.0 |
JESD305-R8-RCE | Apr 2022 |
This standard, JESD305-R8-RCE, DDR5 Registered Dual Inline Memory Module with 8-bit ECC (EC8 RDIMM) Raw Card E Annex, defines the design detail of x8, 2 Package Ranks DDR5 RDIMM with 8-bit ECC. The common feature of DDR5 RDIMM, such as the connector pinout, can be found in the JESD305, DDR5 Load Reduced (LRDIMM) and Registered Dual Inline Memory Module (RDIMM) Common Standard. Item 2273.13. Committee(s): JC-45.1 Free download. Registration or login required. |
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DDR5 RDIMM Standard, Annex FRelease Number: Version 1.0 |
JESD305-R8-RCF | Apr 2022 |
This standard, JESD305-R4-RCF, DDR5 Registered Dual Inline Memory Module with 4-bit ECC (EC4 RDIMM) Raw Card F Annex, defines the design detail of x4, 1 Package Rank DDR5 RDIMM with 4-bit ECC. The common feature of DDR5 RDIMM, such as the connector pinout, can be found in the JESD305, DDR5 Load Reduced (LRDIMM) and Registered Dual Inline Memory Module (RDIMM) Common Standard. Item 2273.10. Committee(s): JC-45.1 Free download. Registration or login required. |
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DDR5 RDIMM Standard, Annex CRelease Number: Version 1.0 |
JESD305-R8-RCC | Apr 2022 |
This standard, JESD305-R8-RCC, DDR5 Registered Dual Inline Memory Module with 8-bit ECC (EC8 RDIMM) Raw Card C Annex, defines the design detail of x4, 1 Package Rank DDR5 RDIMM with 8-bit ECC. The common feature of DDR5 RDIMM, such as the connector pinout, can be found in the JESD305, DDR5 Load Reduced (LRDIMM) and Registered Dual Inline Memory Module (RDIMM) Common Standard. Item 2273.12. Committee(s): JC-45.1 Free download. Registration or login required. |
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BYTE ADDRESSABLE ENERGY BACKED INTERFACE |
JESD245E | Apr 2022 |
This standard specifies the host and device interface for a DDR4 NVDIMM-N, which is a DIMM that achieves non-volatility by copying SDRAM contents into non-volatile memory (NVM) when host power is lost using an Energy Source managed by either the module or the host. This standard is used in conjunction with JESD248. Item 2233.54G Committee(s): JC-45.6 Free download. Registration or login required. |
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DDR5 RDIMM Standard Annex DRelease Number: Version 1.0 |
JESD305-R8-RCD | Apr 2022 |
This standard, JESD305-R8-RCD, DDR5 Registered Dual Inline Memory Module with 8-bit ECC (EC8 RDIMM) Raw Card D Annex, defines the design detail of x8, 1 Package Rank DDR5 RDIMM with 8-bit ECC. The common feature of DDR5 RDIMM, such as the connector pinout, can be found in the JESD305, DDR5 Load Reduced (LRDIMM) and Registered Dual Inline Memory Module (RDIMM) Common Standard. Item 2273.03 Committee(s): JC-45.1 Free download. Registration or login required. |
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DDR5 RDIMM Standard Annex BRelease Number: Version 1.0 |
JESD305-R4-RCB | Apr 2022 |
This standard, JESD305-R4-RCB, DDR5 Registered Dual Inline Memory Module with 4-bit ECC (EC4 RDIMM) Raw Card B Annex, defines the design detail of x4, 2 Package Ranks DDR5 RDIMM with 4-bit ECC. The common feature of DDR5 RDIMM, such as the connector pinout, can be found in the JESD305, DDR5 Load Reduced (LRDIMM) and Registered Dual Inline Memory Module (RDIMM) Common Standard. Item 2273.14. Committee(s): JC-45.1 Free download. Registration or login required. |
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DDR5 RDIMM Standard Annex ARelease Number: Version 1.0 |
JESD305-R8-RCA | Mar 2022 |
Item 2273.16 Committee(s): JC-45.1 Free download. Registration or login required. |
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METHOD FOR DEVELOPING ACCELERATION MODELS FOR ELECTRONIC DEVICE FAILURE MECHANISMS |
JESD91B | Mar 2022 |
The method described in this document applies to all reliability mechanisms associated with electronic devices. The purpose of this standard is to provide a reference for developing acceleration models for defect-related and wear-out mechanisms in electronic devices. Committee(s): JC-14.3 Free download. Registration or login required. |
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Annex F, R/C F, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Registered DIMM Design SpecificationRelease Number: 31 |
MODULE4.20.28.F | Mar 2022 |
This specification defines the electrical and mechanical requirements for Raw Card F, 288-pin, 1.2 Volt (VDD), Registered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM RDIMMs). These DDR4 Registered DIMMs (RDIMMs) are intended for use as main memory when installed in PCs. Item 2241.11B JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Annex D, Raw Card D, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design SpecificationRelease Number: 31 |
MODULE4.20.25.D | Mar 2022 |
This specification defines the electrical and mechanical requirements for Raw Card D, 260-pin, 1.2 Volt (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SO-DIMMs). These DDR4 SO-DIMMs are intended for use as main memory when installed in PCs, laptops, and other systems. Item 2228.60. Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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TEMPERATURE RANGE AND MEASUREMENTS FOR COMPONENTS AND MODULES |
JESD402-1A | Mar 2022 |
This document specifies standard temperature ranges that may be used, by way of referencing JESD402-1, in other standards, specifications, and datasheets when defining temperature related specifications. Items 1855.13, 1855.16, 1855.22, and 1855.24 Committee(s): JC-42 Free download. Registration or login required. |
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Registration - Plastic Dual Small Outline Surface, 2 Terminal, Wettable Flank Package |
MO-343B | Mar 2022 |
Designator: PDSO-N2-I#-R#x#Z#-CturET0p04 Patents(): Nexperia BV: US8809121 B2 Committee(s): JC-11.11 Free download. Registration or login required. |
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Registration - Plastic Dual Small Outline Surface Terminal, Wettable Flank Package |
MO-340C | Mar 2022 |
Designator: PDSO_N#[#]_I#-R#x#Z#-CturET0p04 Patents(): Nexperia BV: 8809121B2 Committee(s): JC-11.11 Free download. Registration or login required. |
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Registration - Plastic Dual Connector |
SO-025B | Mar 2022 |
Designator: PDXC-PP2-I8p9-R107p6xp15Z26p0-DD2p95x1p1 Committee(s): JC-11.14 Free download. Registration or login required. |
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Registration - Enclosure Form Factor for Automotive SSD Connector, Board Mount |
SO-030A | Feb 2022 |
Designator: PBCX-K4_... Cross Reference: MO-348 Committee(s): JC-11.14 Free download. Registration or login required. |
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Registration - 262 Pin DDR5 SODIMM, 0.50 mm Pitch Package |
MO-337B | Feb 2022 |
Designator: PDMA-N262-I0p5-R69p6x3p7Z30p15R2p55x02p35 Item: 11.14-207, Access STP Files for MO-337B Cross Reference: SO-024 Committee(s): JC-11.14 Free download. Registration or login required. |
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Registration - 288 Pin DDR5 DIMM, 0.85 mm Pitch Microelectronic Assembly |
MO-329E | Jan 2022 |
Designator: PDMA-N288-I0p85-R133p8x#p#7Z31p8R2p55x0p6 Patents(): Micron: US7,547,213. Committee(s): JC-11.14 Free download. Registration or login required. |
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DDR5 Load Reduced (LRDIMM) and Registered Dual Inline Memory Module (RDIMM) Common Specification |
JESD305 | Jan 2022 |
This standard defines the electrical and mechanical requirements for 288-pin, 1.1 Volt (VDD and VDDQ), DDR5 Registered (RDIMM) and Load Reduced (LRDIMM), Double Data Rate (DDR), Synchronous DRAM Dual In-Line Memory Modules (DIMM). These 288-pin Registered and Load Reduced DDR5 SDRAM DIMMs are intended for use in server, workstation, and database environments. Item 2273.07. Committee(s): JC-45.1 Free download. Registration or login required. |
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TEST METHOD FOR THE MEASUREMENT OF MOISTURE DIFFUSIVITY AND WATER SOLUBILITY IN ORGANIC MATERIALS USED IN ELECTRONIC DEVICES |
JESD22-A120C | Jan 2022 |
This standard details the procedures for the measurement of characteristic bulk material properties of moisture diffusivity and water solubility in organic materials used in the packaging of electronic devices. These two material properties are important parameters for the effective reliability performance of plastic packaged surface mount devices after exposure to moisture and subjected to high temperature solder reflow. Committee(s): JC-14.1 Free download. Registration or login required. |
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High Bandwidth Memory DRAM (HBM3) |
JESD238 | Jan 2022 |
The HBM3 DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM3 DRAM uses a wide-interface architecture to achieve high-speed, low power operation. Each channel interface maintains a 64 bit data bus operating at double data rate (DDR). Item 1837.98. Committee(s): JC-42.2 Free download. Registration or login required. |
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STANDARD MANUFACTURERS IDENTIFICATION CODENOTE: JEP106U was in error starting with bank two an additional continuation code was added, JEP106U should be discarded. |
JEP106BE | Jan 2022 |
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to http://www.jedec.org/Home/MIDCODE_request.cfm Free download. Registration or login required. |
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Registration - Enclosure Form Factor for Automotive SSD Connector, Cable Mount |
SO-029A | Jan 2022 |
Designator: PBXC-K4_D#p##-MR36p05x14p5Z10p25-HS Cross Reference: MO-348 Committee(s): JC-11.14 Free download. Registration or login required. |
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IC LATCH-UP TEST |
JESD78F | Jan 2022 |
This standard covers the I-test and Vsupply overvoltage latch-up testing of integrated circuits. The purpose of this standard is to establish a method for determining IC latch-up characteristics and to define latch-up detection criteria. Latch-up characteristics are extremely important in determining product reliability and minimizing No Trouble Found (NTF) and Electrical Overstress (EOS) failures due to latch-up. This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies. This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880. Committee(s): JC-14.1 Free download. Registration or login required. |
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Test Procedure for the Measurement of Terrestrial Cosmic Ray Induced Destructive Effects in Power Semiconductor Devices |
JEP151A | Jan 2022 |
This test method defines the requirements and procedures for terrestrial destructive* single-event effects (SEE) for example, single-event breakdown (SEB), single-event latch-up (SEL) and single-event gate rupture (SEGR) testing . It is valid when using an accelerator, generating a nucleon beam of either; 1) Mono-energetic protons or mono-energetic neutrons of at least 150 MeV energy, or 2) Neutrons from a spallation spectrum with maximum energy of at least 150 MeV. This test method does not apply to testing that uses beams with particles heavier than protons. *This test method addresses a separate risk than does JESD89 tests for non-destructive SEE due to cosmic radiation effects on terrestrial applications.
Committee(s): JC-14.1 Free download. Registration or login required. |
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SERIAL INTERFACE FOR DATA CONVERTERS |
JESD204C.01 | Jan 2022 |
This is a minor editorial change to JESD204C, the details can be found in Annex A. This standard describes a serialized interface between data converters and logic devices. It contains normative information to enable designers to implement devices that communicate with other devices covered by this document. Informative sections are included to clarify and exemplify the standard. Item 192.02B. Committee(s): JC-16 Free download. Registration or login required. |
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DDR5 Buffer Definition (DDR5DB01) - Rev. 1.1 |
JESD82-521 | Dec 2021 |
This standard defines standard specifications for features and functionality, DC & AC interface parameters and test loading for definition of the DDR5 data buffer for driving DQ and DQS nets on DDR5 LRDIMM applications. The purpose is to provide a standard for the DDR5DB01 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Item 323.98K Committee(s): JC-40.4 Free download. Registration or login required. |
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Backup Energy Module Standard for NVDIMM Memory Devices (BEM) |
JESD315 | Dec 2021 |
This standard defines the functional requirements of Backup Energy Module (BEM), henceforth referred to as BEM in this standard. This module shall be used to provide backup power to the Industry Defined Storage Array Controller Cards and NVDIMM-n as applicable. All standards are applicable under all operating conditions unless otherwise stated. Item 2279.03 Committee(s): JC-45 Free download. Registration or login required. |
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Guidelines for Representing Switching Losses of SIC MOSFETs in Datasheets |
JEP187 | Dec 2021 |
This document describes the impact of measurement and/or setup parameters on switching losses of power semiconductor switches; focusing primarily on SiC MOSFET turn-on losses. In terms of turn-off losses, the behavior of SiC MOSFETs is similar to that of existing silicon based power MOSFETs, and as such are adequately represented in typical datasheets. Committee(s): JC-70.2 Free download. Registration or login required. |
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Guideline to Specify a Transient Off-State Withstand Voltage Robustness Indicator in Datasheets for Lateral GaN Power Conversion Devices, Version 1.0 |
JEP186 | Dec 2021 |
This guideline describes different techniques for specifying a Transient Off-state Withstand Voltage Robustness Indicator in datasheets for lateral GaN power conversion devices. This guideline does not convey preferences for any of the specification types presented, nor does the guideline address formatting of datasheets. This guideline does not indicate nor require that the datasheet parameters are used in production tests, nor specify how the values were obtained. Committee(s): JC-70.1 Free download. Registration or login required. |
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JEDEC MODULE SIDEBAND BUS (SidebandBus) |
JESD403-1A | Dec 2021 |
This standard defines the assumptions for the system management bus for next generation memory solutions; covering the interface protocol, use of hub devices, and voltages appropriate to these usages. Item 2260.56. Committee(s): JC-45 Free download. Registration or login required. |