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This document defines the JC-42.6 Manufacturer ID. This document covers Manufacturer ID Codes for the following technologies: LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), LPDDR4 (JESD209-4), Wide-IO (JESD229), and Wide-IO2 (JESD229-2). The purpose of this document is to define the Manufacturer ID for these devices. Item No. 1725.03C. See Annex for additions/changes. To make a request for an ID code: https://www.jedec.org/id-codes-low-power-memories

Committee(s): JC-42.6

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This document is intended to guide device manufacturers in developing datasheets and to device customers in understanding datasheet entries.

Committee(s): JC-14.3

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The scope of this document covers SiC-based PECS devices having a gate dielectric region biased to turn devices on and off. This typically refers to MOS devices such as MOSFETs and IGBTs. In this document, only NMOS devices are discussed as these are dominant for power device applications; however, the procedures apply to PMOS devices as well.

Committee(s): JC-70.2

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Designator: PBMA-N32[39]_Ip0-R14p1x18p1Z1p65-R0p71x1p1 
Item: 11.11-987, Access STP Files for MO-347A
Cross Reference: N/A

Patents(): Kioxia: 1705380

Committee(s): JC-11.11

JEP95 Registrations Main Page

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A DRAM rowhammer security exploit is a serious threat to cloud service providers, data centers, laptops, smart phones, self-driving cars and IoT devices. Hardware research and development will take time. DRAM components, DRAM DIMMs, System-on-chip (SoC), chipsets and system products have their own design cycle time and overall life time. This publication recommends best practices to mitigate the security risks from rowhammer attacks. Item 1866.02.

Committee(s): JC-42

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The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achieve high-speed, low-power operation. The HBM DRAM uses differential clock CK_t/CK_c. Commands are registered at the rising edge of CK_t, CK_c. Each channel interface maintains a 128b data bus operating at DDR data rates. Also available for designer ease of use is HBM Ballout Spreadsheet (Note this version is the latest version for use with JESD235D). Committee item 1797.99L.

Committee(s): JC-42.3C

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This document defines the 3DS DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a compliant 8 Gbit through 128 Gbit for x4, x8 3DS DDR4 SDRAM devices. This addendum was created based on the JESD79-4 DDR4 SDRAM specification. Each aspect of the changes for 3DS DDR4 SDRAM operation was considered. Item 1727.58G

Committee(s): JC-42.3C

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Designator: PDSO-G#_I0P##-##...

Item 11.11-990

Committee(s): JC-11.11

JEP95 Registrations Main Page

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This version is a minor editorial adding Annex B that was left out of the original publication October 2020.An NVDIMM-P device is defined as a LRDIMM memory module which provides host controller access to DRAM and/or other memory devices such as persistent memory.  A transactional protocol is described for NVDIMM-P, which may be used on a DDR interface allowing operation of both standard DRAM modules and NVDIMM-P modules on the same channel. Item 2233.98K.

Committee(s): JC-45.6

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This standard identifies the best commercial practices for mitigating and/or avoiding counterfeit products by all manufacturers of electronic parts including, but not limited to original component manufacturers (OCMs), authorized aftermarket manufacturers, and other companies that manufacture electronic parts under their own logo, name, or trademark. The types of product this standard applies to is limited to monolithic microcircuits, hybrid microcircuits and discrete semiconductor products.

Committee(s): JC-13

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This document is intended for use in the GaN power semiconductor and related power electronic industries and provides guidelines for test methods and circuits to be used for continuous-switching tests of GaN power conversion devices.

Committee(s): JC-70.1

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This document, while establishing the complex nature of System Level ESD, proposes that an efficient ESD design can only be achieved when the interaction of the various components under ESD conditions are analyzed at the system level. This objective requires an appropriate characterization of the components and a methodology to assess the entire system using simulation data. This is applicable to system failures of different categories (such as hard, soft, and electromagnetic interference (EMI)). This type of systematic approach is long overdue and represents an advanced design approach which replaces the misconception, as discussed in detail in JEP161, that a system will be sufficiently robust if all components exceed a certain ESD level.

Committee(s): JC-14, JC-14.3

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Designator: PBGA-B#[#]_I80...
Item: 11.11-989, Access STP File for MO-216G
Cross Reference: DR4.5

Committee(s): JC-11.11

JEP95 Registrations Main Page

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This standard was created to facilitate the procurement and use of high reliability semiconductor microcircuits or discrete devices provided in bare die form, commonly known as Known Good Die (KGD).

Committee(s): JC-13

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This specification defines the electrical and mechanical requirements for Raw Card D, 288-pin, 1.2 Volt (VDD), Load Reduced, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM LRDIMMs). These DDR4 Load Reduced DIMMs (LRDIMMs) are intended for use as main memory when installed in PCs. Item 2204.23

Committee(s): JC-45.4

JESD21-C Solid State Memory Documents Main Page

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This document defines the electrical and mechanical requirements for Raw Card B, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Item 2231.26.

Committee(s): JC-45.3

JESD21-C Solid State Memory Documents Main Page

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This specification defines the electrical and mechanical requirements for Raw Card E, 288-pin, 1.2 Volt (VDD), Load Reduced, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM LRDIMMs). These DDR4 Load Reduced DIMMs (LRDIMMs) are intended for use as main memory when installed in PCs. Item 2232.20.

Committee(s): JC-45.4

JESD21-C Solid State Memory Documents Main Page

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This document defines the electrical and mechanical requirements for Raw Card A, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Committee Item 2231.38A.

Committee(s): JC-45.3

JESD21-C Solid State Memory Documents Main Page

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This annex describes the serial presence detect (SPD) values for all DDR4 modules covered in Document Release 6. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. Item 2220.01H. 

Committee(s): JC-45

JESD21-C Solid State Memory Documents Main Page

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