Global Standards for the Microelectronics Industry
Standards & Documents Search
| Title | Document # |
Date |
|---|---|---|
DDR5 Load Reduced (LRDIMM) and Registered Dual Inline Memory Module (RDIMM) Common Specification |
JESD305 | Jan 2022 |
This standard defines the electrical and mechanical requirements for 288-pin, 1.1 Volt (VDD and VDDQ), DDR5 Registered (RDIMM) and Load Reduced (LRDIMM), Double Data Rate (DDR), Synchronous DRAM Dual In-Line Memory Modules (DIMM). These 288-pin Registered and Load Reduced DDR5 SDRAM DIMMs are intended for use in server, workstation, and database environments. Item 2273.07. Committee(s): JC-45.1 Free download. Registration or login required. |
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TEST METHOD FOR THE MEASUREMENT OF MOISTURE DIFFUSIVITY AND WATER SOLUBILITY IN ORGANIC MATERIALS USED IN ELECTRONIC DEVICES |
JESD22-A120C | Jan 2022 |
This standard details the procedures for the measurement of characteristic bulk material properties of moisture diffusivity and water solubility in organic materials used in the packaging of electronic devices. These two material properties are important parameters for the effective reliability performance of plastic packaged surface mount devices after exposure to moisture and subjected to high temperature solder reflow. Committee(s): JC-14.1 Free download. Registration or login required. |
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High Bandwidth Memory DRAM (HBM3) |
JESD238 | Jan 2022 |
The HBM3 DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM3 DRAM uses a wide-interface architecture to achieve high-speed, low power operation. Each channel interface maintains a 64 bit data bus operating at double data rate (DDR). Item 1837.98. Committee(s): JC-42.2 Free download. Registration or login required. |
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TS5111, TS5110 Serial Bus Thermal Sensor Device Standard |
JESD302-1 | Jan 2022 |
This standard defines the specifications of interface parameters, signaling protocols, and features for fifth generation Temperature Sensor (TS5) as used for memory module applications. These device operate on I2C and I3C two-wire serial bus interface. The designation TS5111 and TS5110 refers to the device specified by this document. Item 401.01E Committee(s): JC-40.1 Free download. Registration or login required. |
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STANDARD MANUFACTURERS IDENTIFICATION CODENOTE: JEP106U was in error starting with bank two an additional continuation code was added, JEP106U should be discarded. |
JEP106BE | Jan 2022 |
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to http://www.jedec.org/Home/MIDCODE_request.cfm Free download. Registration or login required. |
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Registration - Enclosure Form Factor for Automotive SSD Connector, Cable Mount |
SO-029A | Jan 2022 |
Designator: PBXC-K4_D#p##-MR36p05x14p5Z10p25-HS Cross Reference: MO-348 Committee(s): JC-11.14 Free download. Registration or login required. |
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IC LATCH-UP TEST |
JESD78F | Jan 2022 |
This standard covers the I-test and Vsupply overvoltage latch-up testing of integrated circuits. The purpose of this standard is to establish a method for determining IC latch-up characteristics and to define latch-up detection criteria. Latch-up characteristics are extremely important in determining product reliability and minimizing No Trouble Found (NTF) and Electrical Overstress (EOS) failures due to latch-up. This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies. This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880. Committee(s): JC-14.1 Free download. Registration or login required. |
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Test Procedure for the Measurement of Terrestrial Cosmic Ray Induced Destructive Effects in Power Semiconductor Devices |
JEP151A | Jan 2022 |
This test method defines the requirements and procedures for terrestrial destructive* single-event effects (SEE) for example, single-event breakdown (SEB), single-event latch-up (SEL) and single-event gate rupture (SEGR) testing . It is valid when using an accelerator, generating a nucleon beam of either; 1) Mono-energetic protons or mono-energetic neutrons of at least 150 MeV energy, or 2) Neutrons from a spallation spectrum with maximum energy of at least 150 MeV. This test method does not apply to testing that uses beams with particles heavier than protons. *This test method addresses a separate risk than does JESD89 tests for non-destructive SEE due to cosmic radiation effects on terrestrial applications.
Committee(s): JC-14.1 Free download. Registration or login required. |
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SERIAL INTERFACE FOR DATA CONVERTERS |
JESD204C.01 | Jan 2022 |
This is a minor editorial change to JESD204C, the details can be found in Annex A. This standard describes a serialized interface between data converters and logic devices. It contains normative information to enable designers to implement devices that communicate with other devices covered by this document. Informative sections are included to clarify and exemplify the standard. Item 192.02B. Committee(s): JC-16 Free download. Registration or login required. |
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DDR5 Buffer Definition (DDR5DB01) - Rev. 1.1 |
JESD82-521 | Dec 2021 |
This standard defines standard specifications for features and functionality, DC & AC interface parameters and test loading for definition of the DDR5 data buffer for driving DQ and DQS nets on DDR5 LRDIMM applications. The purpose is to provide a standard for the DDR5DB01 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Item 323.98K Committee(s): JC-40.4 Free download. Registration or login required. |
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Backup Energy Module Standard for NVDIMM Memory Devices (BEM) |
JESD315 | Dec 2021 |
This standard defines the functional requirements of Backup Energy Module (BEM), henceforth referred to as BEM in this standard. This module shall be used to provide backup power to the Industry Defined Storage Array Controller Cards and NVDIMM-n as applicable. All standards are applicable under all operating conditions unless otherwise stated. Item 2279.03 Committee(s): JC-45 Free download. Registration or login required. |
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Guidelines for Representing Switching Losses of SIC MOSFETs in Datasheets |
JEP187 | Dec 2021 |
This document describes the impact of measurement and/or setup parameters on switching losses of power semiconductor switches; focusing primarily on SiC MOSFET turn-on losses. In terms of turn-off losses, the behavior of SiC MOSFETs is similar to that of existing silicon based power MOSFETs, and as such are adequately represented in typical datasheets. Committee(s): JC-70.2 Free download. Registration or login required. |
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Guideline to Specify a Transient Off-State Withstand Voltage Robustness Indicator in Datasheets for Lateral GaN Power Conversion Devices, Version 1.0 |
JEP186 | Dec 2021 |
This guideline describes different techniques for specifying a Transient Off-state Withstand Voltage Robustness Indicator in datasheets for lateral GaN power conversion devices. This guideline does not convey preferences for any of the specification types presented, nor does the guideline address formatting of datasheets. This guideline does not indicate nor require that the datasheet parameters are used in production tests, nor specify how the values were obtained. Committee(s): JC-70.1 Free download. Registration or login required. |
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SERIAL FLASH DISCOVERABLE PARAMETERS (SFDP) |
JESD216F | Dec 2021 |
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. Any company may request a Function Specific ID by making a request to the JEDEC office at juliec@jedec.org. Please include “Function Specific ID Request, JESD216” in the email subject line. Item 1775.73. Committee(s): JC-42.4 Free download. Registration or login required. |
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JEDEC MODULE SIDEBAND BUS (SidebandBus) |
JESD403-1A | Dec 2021 |
This standard defines the assumptions for the system management bus for next generation memory solutions; covering the interface protocol, use of hub devices, and voltages appropriate to these usages. Item 2260.56. Committee(s): JC-45 Free download. Registration or login required. |
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Registration - Plastic Bottom Grid Array Ball, 0.35 mm x 0.40 mm Pitch Rectangular Family Package |
MO-350A | Nov 2021 |
Designator: PBGA-B#[#]_I0p35...Item 11-998 Committee(s): JC-11.11 Free download. Registration or login required. |
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Registration - Silicon Bottom Grid Array Column, 0.048 mm x 0.055 mm Pitch Square Package |
MO-349A | Nov 2021 |
Designator: SBGA-M7775[23828]_D0p073... Item: 11.4-996 Access STP Files for MO-349ACross Reference: DR4.26 Committee(s): JC-11.4 Free download. Registration or login required. |
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SEMICONDUCTOR WAFER AND DIE BACKSIDE EXTERNAL VISUAL INSPECTION |
JESD22-B118A | Nov 2021 |
This inspection method is for product semiconductor wafers and dice prior to assembly. This test method defines the requirements to execute a standardized external visual inspection and is a non-invasive and nondestructive examination that can be used for qualification, quality monitoring, and lot acceptance. Committee(s): JC-14.1 Free download. Registration or login required. |
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DEFINITION OF THE SSTUA32S865 AND SSTUA32D865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS |
JESD82-19A.01 | Oct 2021 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUA32S865 and SSTUA32D865 registered buffer with parity for 2 rank by 4 or similar high-density DDR2 RDIMM applications. This is a minor editor revision as shown in Annex A of the document. Committee(s): JC-40 Free download. Registration or login required. |
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DEFINITION OF THE SSTU32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS |
JESD82-10A.01 | Oct 2021 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTU32866 registered buffer with parity test for DDR2 RDIMM applications. The purpose is to provide a standard for the SSTU32866 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor editorial revision as shown in Annex A of the document. Free download. Registration or login required. |
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