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Title	Document #	Date
APPLICATION THERMAL DERATING METHODOLOGIES:	JEP149.01	Jan 2021
This publication applies to the application of integrated circuits and their associated packages in end use designs. It summarizes the methodology of thermal derating and the suitability of such methodologies. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
GUIDELINES FOR REPORTING AND USING ELECTRONIC PACKAGE THERMAL INFORMATION	JESD51-12.01	Nov 2012
This document provides guidelines for both reporting and using electronic package thermal information generated using JEDEC JESD51 standards. By addressing these two areas, this document can be used as the common basis for discussion between electronic package thermal information suppliers and users. Committee(s): JC-15, JC-15.1 Free download. Registration or login required.
EXTENSION TO JESD51 THERMAL TEST BOARD STANDARDS TO ACCOMMODATE MULTI-CHIP PACKAGES	JESD51-32	Dec 2010
This document addresses the need for extending the existing thermal test board standards to accommodate the potential of higher electrical connection needs of multi-chip packages (MCPs) and the associated wire routing to implement these connections. The extensions described in this standard are also applicable to single chip packages needing more than 36 electrical connections for the test. Committee(s): JC-15 Free download. Registration or login required.
TS3000 Standalone Thermal Sensor Component	SPD4.1.5	Nov 2009
Release No. 19A, Item 1640.11 Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - Small Scale, Plastic, Ultra, Extra, and Super Thin, Fine Pitch, Quad Flat No Lead Package (with Optional Thermal Enhancements). (U, X1, X2)F-PQFN & H(U, X1, X2)F-PQFN.	MO-288-B	Sep 2009
Item 11.11-821 Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.

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