Global Standards for the Microelectronics Industry
Standards & Documents Search
Title | Document # |
Date![]() |
---|---|---|
DDR Specific SDRAM Functions |
SDRAM3.11.5.2 | Jun 2003 |
Release No. 13 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
||
200 Pin, PC-2700/PC-2100/PC-1600 Unbuffered SO-DIMM SDRAM Reference Design Specification |
MODULE4.20.6 | Oct 2003 |
Release No. 13 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
||
SPD Annex D, DDR Synchronous DRAM (DDR SDRAM) |
SPD4.1.2.4 | Jan 2004 |
Release No.13 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
||
100-Pin DDR SDRAM Unbuffered 32b-DIMM Design Specification |
MODULE4.20.9 | Nov 2004 |
Release No. 14 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
||
DRIVER SPECIFICATIONS FOR 1.8 V POWER SUPPLY POINT-TO-POINT DRIVERS |
JESD8-17 | Nov 2004 |
This material is intended to be reflected in supplier specifications for point to point DDR devices ranging from 400 Mb/s to 800 Mb/s operation. It is a method to specify driver impedance with something other than a number that does not nec-essarily define how it operates in a real net This standard addresses this issue using net lengths and specifies how much uncertainty can exist in the data for each speed supported. Free download. Registration or login required. |
||
DEFINITION OF THE SSTV32852 2.5 V 24-BIT TO 48-BIT SSTL_2 REGISTERED BUFFER FOR 1U STACKED DDR DIMM APPLICATIONS: |
JESD82-6A | Nov 2004 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV32852 24-bit to 48-bit SSTL_2 registered buffer for stacked DDR DIMM applications. The purpose is to provide a standard for the SSTV32852 logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required. |
||
DDR2 Specific SDRAM Function |
SDRAM3.11.5.5 | Jul 2008 |
Release No. 18 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
||
Addendum No. 1 to JESD209A, LOW POWER DOUBLE DATA RATE (LPDDR) SDRAM, 1.2 V I/O. |
JESD209A-1 | Mar 2009 |
This document defines the Low Power Double Data Rate (LPDDR) SDRAM 1.2 V I/O, including AC and DC operating conditions, extended mode register settings, and I-V characteristics. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 64 Mb through 2 Gb for x16 and x32 Low Power Double Data Rate SDRAM devices with 1.2 V I/O. System designs based on the required aspects of this specification will be supported by all LPDDR SDRAM vendors providing compliant devices. Committee(s): JC-42.6 Free download. Registration or login required. |
||
LOW POWER DOUBLE DATA RATE (LPDDR) SDRAM STANDARD |
JESD209B | Feb 2010 |
This standard defines the Low Power Double Data Rate (LPDDR) SDRAM, including features, functionality, AC and DC characteristics, packages, and pin assignments. This scope may be expanded in future to also include other higher density devices. The purpose of this document is to define the minimum set of requirements for JEDEC compliant 64Mb through 2Gb for x16 and x32 Low Power Double Data Rate SDRAM devices. System designs based on the required aspects of this standard will be supported by all LPDDR SDRAM vendors providing compliant devices. (JESD209 was originally numbered as JESD79-4 May 2006 to August 2007, corrected to JESD209 09/17/2007). Patents(): See Document Committee(s): JC-42.3, JC-42.6 Free download. Registration or login required. |
||
Registration - DDR2 SDRAM DIMM (Dual Inline Memory Module) Family with 1.00 mm Contact Centers. |
MO-237-G.01 | Apr 2011 |
Item 11.14-128, 11.14-128E Patents(): Hitachi: 5,227,664 Committee(s): JC-11.14 Free download. Registration or login required. |
||
DDR3 SDRAM STANDARD |
JESD79-3F | Jul 2012 |
This document defines the DDR3 SDRAM standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 512 Mb through 8 Gb for x4, x8, and x16 DDR3 SDRAM devices. This document was created based on the DDR2 standard (JESD79-2) and some aspects of the DDR standard (JESD79). Each aspect of the changes for DDR3 SDRAM operation were considered and approved by committee ballots). The accumulation of these ballots were then incorporated to prepare this standard (JESD79-3), replacing whole sections and incorporating the changes into Functional Description and Operation. Item 1627.14 Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42.3 Available for purchase: $247.00 Add to Cart Paying JEDEC Members may login for free access. |
||
SPD Annex K - Serial Presence Detect (SPD) for DDR3 SDRAM Modules, Release 6 |
SPD4.1.2.11 | Feb 2014 |
Release No. 24. Item 2065.47A Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
||
240-Pin PC2-5300/PC2-6400 DDR2 SDRAM Unbuffered DIMM Design Specification |
MODULE4.20.13 | May 2021 |
Release 31. Item 2167.05This revision contains terminology updates only. Committee(s): JC-45, JC-45.2, JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
||
240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Unbuffered DIMM Design Specification |
MODULE4.20.19 | May 2021 |
Release No. 31. Item 2131.03, 2078.04, 2131.06This revision contains terminology updates only. Committee(s): JC-45, JC-45.2, JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
||
184 Pin Unbuffered DDR SDRAM DIMM |
MODULE4.5.10 | May 2021 |
Release No.31This revision contains terminology updates only. JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |