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Title	Document #	Date
STANDARD FOR DEFINITION OF THE CUA877 AND CU2A877 PLL CLOCK DRIVERS FOR REGISTERED DDR2 DIMM APPLICATIONS	JESD82-18A	Jan 2007
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the CUA877 and CU2A877 PLL clock devices for registered DDR2 DIMM applications.The purpose is to provide a standard for the CUA877 and CU2A877 PLL clock devices, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required.
STANDARD FOR DEFINITION OF CUA878 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS	JESD82-15	Nov 2005
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CUA878 PLL clock device for registered DDR2 DIMM applications. The purpose is to provide a standard for a CUA878 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required.
STANDARD FOR DEFINITION OF CUA845 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS	JESD82-21	Jan 2007
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CUA845 PLL clock device for registered DDR2 DIMM applications.The purpose is to provide a standard for a CUA845 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required.
STANDARD FOR DEFINITION OF CU877 PLL CLOCK DRIVE FOR REGISTERED DDR2 DIMM APPLICATION	JESD82-8.01	Feb 2004
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a íCU877 PLL clock device for registered DDR2 DIMM applications. The purpose is to provide a standard for a íCU877 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This document includes minor editorial changes as noted in Annex A, page 16. Committee(s): JC-40 Free download. Registration or login required.
Standard - SMT DDR2 DIMM Socket, Coplanarity Measurement Gauge. Item 11.14-102.	GS-006-A	Jun 2007
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Standard - DDR2 DIMM Socket Insertion and Extraction Force Gauge. Item 11.14-103.	GS-007-A	Jun 2007
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
SPECIALITY DDR2-1066 SDRAM	JESD208	Nov 2007
This document defines the Specialty DDR2-1066 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Specification is to define the minimum set of requirements for JEDEC compliant 256 Mb through 4 Gb for x4, x8, and x16 Specialty DDR2-1066 SDRAM devices. Committee(s): JC-42.3 Free download. Registration or login required.
SPD Annex J: Serial Presence Detect for DDR2 SDRAM	SPD4.1.2.10	Jan 2007
Release No. 17 Committee(s): JC-42, JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SPD Annex G, Serial Presence Detect for FBDIMM, Revision 1.1	SPD4.1.2.7	Jun 2006
Release No. 16A. Item 2003.02A Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - DDR2 SDRAM DIMM (Dual Inline memory Module) Family, Flex-Based, 1.00 mm Contact Centers.	MO-281-A	Nov 2006
Item 11.14-100 Patents(): STAKTEK: See Outline Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - DDR2 DIMM 240 Pin SMT Socket Outline with 1.00 mm Contact Centers. Item 11.14-097.	SO-009A	Feb 2007
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - DDR1/DDR2/DDR3, 144 Pin, 16b/32b Small Outline Dual Inline Memory Module (SODIMM), 0.8 mm Pitch, Socket Outline.	SO-008B	Oct 2012
Item 11.14-141 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - DDR and DDR2 Micro DIMM Mezzanine, 214 pin, 0.4 mm Lead Centers.	MO-260-C	Dec 2006
Item 11.14-101 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Connector Outline for DDR and DDR2 Micro DIMM Mezzanine, 214 pin, 0.4 mm Lead Centers. Item 11.14-076.	SO-004A	May 2005
Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 244 Pin DDR2/DDR3 Mini Dual-In-Line Memory Module (DIMM) Family, 0.60 mm Lead Centers.	MO-244D	Jul 2012
Item No. 14-136 Patents(): Hitachi: 5,227,664 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 244 Pin DDR2/DDR3 Mini DIMM with 0.60 mm Lead Centers Socket Outline. Item 11.14-122.	SO-002B	Oct 2003
Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 240 Pin DDR2 DIMM 1.00 mm Contact Centers, Press Fit Socket Outline. Item 11.14-111	SO-011A	Sep 2007
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
PC2-4200/PC2-3200 DDR2 Registered Mini-DIMM Design Specification Revision 2.0	MODULE4.20.14	Dec 2006
Release No. 16. Item 2105.00 Committee(s): JC-45, JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
FBDIMM: ADVANCED MEMORY BUFFER (AMB)	JESD82-20A.01	Jan 2023
This document is a core specification for a Fully Buffered DIMM (FBD) memory system. This document, along with the other core specifications, must be treated as a whole. Information critical to a Advanced Memory Buffer design appears in the other specifications, with specific cross-references provided. Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-40 Free download. Registration or login required.
FBDIMM SPECIFICATION: HIGH SPEED DIFFERENTIAL PTP LINK AT 1.5 V	JESD8-18A	Mar 2008
This specification defines the high-speed differential point-to-point signaling link for FBDIMM, operating at the buffer supply voltage of 1.5V that is provided at the FBDIMM DIMM connector. This specification also applies to FBDIMM host chips which may operate with a different supply voltage. The link consists of a transmitter and a receiver and the interconnect in between them. The transmitter sends serialized bits into a lane and the receiver accepts the electrical signals of the serialized bits and transforms them into a serialized bit-stream. The first generation FBDIMM link is being specified to operate from 3.2 to 4.8 Gb/s. The specifications are defined for three distinct bit-rates of operation: 3.2 Gb/s, 4.0 Gb/s and 4.8 Gb/s. Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-16 Free download. Registration or login required.

Standards & Documents Search

STANDARD FOR DEFINITION OF THE CUA877 AND CU2A877 PLL CLOCK DRIVERS FOR REGISTERED DDR2 DIMM APPLICATIONS

STANDARD FOR DEFINITION OF CUA878 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS

STANDARD FOR DEFINITION OF CUA845 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS

STANDARD FOR DEFINITION OF CU877 PLL CLOCK DRIVE FOR REGISTERED DDR2 DIMM APPLICATION

Standard - SMT DDR2 DIMM Socket, Coplanarity Measurement Gauge. Item 11.14-102.

Standard - DDR2 DIMM Socket Insertion and Extraction Force Gauge. Item 11.14-103.

SPECIALITY DDR2-1066 SDRAM

SPD Annex J: Serial Presence Detect for DDR2 SDRAM

SPD Annex G, Serial Presence Detect for FBDIMM, Revision 1.1

Registration - DDR2 SDRAM DIMM (Dual Inline memory Module) Family, Flex-Based, 1.00 mm Contact Centers.

Registration - DDR2 DIMM 240 Pin SMT Socket Outline with 1.00 mm Contact Centers. Item 11.14-097.

Registration - DDR1/DDR2/DDR3, 144 Pin, 16b/32b Small Outline Dual Inline Memory Module (SODIMM), 0.8 mm Pitch, Socket Outline.

Registration - DDR and DDR2 Micro DIMM Mezzanine, 214 pin, 0.4 mm Lead Centers.

Registration - Connector Outline for DDR and DDR2 Micro DIMM Mezzanine, 214 pin, 0.4 mm Lead Centers. Item 11.14-076.

Registration - 244 Pin DDR2/DDR3 Mini Dual-In-Line Memory Module (DIMM) Family, 0.60 mm Lead Centers.

Registration - 244 Pin DDR2/DDR3 Mini DIMM with 0.60 mm Lead Centers Socket Outline. Item 11.14-122.

Registration - 240 Pin DDR2 DIMM 1.00 mm Contact Centers, Press Fit Socket Outline. Item 11.14-111

PC2-4200/PC2-3200 DDR2 Registered Mini-DIMM Design Specification Revision 2.0

FBDIMM: ADVANCED MEMORY BUFFER (AMB)

FBDIMM SPECIFICATION: HIGH SPEED DIFFERENTIAL PTP LINK AT 1.5 V

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