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Registration - DDR2 DIMM 240 Pin SMT Socket Outline with 1.00 mm Contact Centers. Item 11.14-097.

 SO-009A Feb 2007

Committee(s): JC-11

JEP95 Registrations Main Page

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Registration - DDR1/DDR2/DDR3, 144 Pin, 16b/32b Small Outline Dual Inline Memory Module (SODIMM), 0.8 mm Pitch, Socket Outline.

SO-008B Oct 2012

Item 11.14-141

Committee(s): JC-11, JC-11.14

JEP95 Registrations Main Page

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Registration - DDR and DDR2 Micro DIMM Mezzanine, 214 pin, 0.4 mm Lead Centers.

MO-260-C Dec 2006

Item 11.14-101

Committee(s): JC-11, JC-11.14

JEP95 Registrations Main Page

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Registration - Connector Outline for DDR and DDR2 Micro DIMM Mezzanine, 214 pin, 0.4 mm Lead Centers. Item 11.14-076.

 SO-004A May 2005

Committee(s): JC-11, JC-11.14

JEP95 Registrations Main Page

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Registration - 244 Pin DDR2/DDR3 Mini Dual-In-Line Memory Module (DIMM) Family, 0.60 mm Lead Centers.

 MO-244D Jul 2012

Item No. 14-136

Patents(): Hitachi: 5,227,664

Committee(s): JC-11, JC-11.14

JEP95 Registrations Main Page

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Registration - 244 Pin DDR2/DDR3 Mini DIMM with 0.60 mm Lead Centers Socket Outline. Item 11.14-122.

 SO-002B Oct 2003

Committee(s): JC-11, JC-11.14

JEP95 Registrations Main Page

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Registration - 240 Pin DDR2 DIMM 1.00 mm Contact Centers, Press Fit Socket Outline. Item 11.14-111

 SO-011A Sep 2007

Committee(s): JC-11

JEP95 Registrations Main Page

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PC2-4200/PC2-3200 DDR2 Registered Mini-DIMM Design Specification Revision 2.0

 MODULE4.20.14 Dec 2006

Release No. 16. Item 2105.00

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

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FBDIMM: ADVANCED MEMORY BUFFER (AMB)

 JESD82-20A.01 Jan 2023

This document is a core specification for a Fully Buffered DIMM (FBD) memory system. This document, along with the other core specifications, must be treated as a whole. Information critical to a Advanced Memory Buffer design appears in the other specifications, with specific cross-references provided.

Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents.

Committee(s): JC-40

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FBDIMM SPECIFICATION: HIGH SPEED DIFFERENTIAL PTP LINK AT 1.5 V

 JESD8-18A Mar 2008

This specification defines the high-speed differential point-to-point signaling link for FBDIMM, operating at the buffer supply voltage of 1.5V that is provided at the FBDIMM DIMM connector. This specification also applies to FBDIMM host chips which may operate with a different supply voltage. The link consists of a transmitter and a receiver and the interconnect in between them. The transmitter sends serialized bits into a lane and the receiver accepts the electrical signals of the serialized bits and transforms them into a serialized bit-stream. The first generation FBDIMM link is being specified to operate from 3.2 to 4.8 Gb/s. The specifications are defined for three distinct bit-rates of operation: 3.2 Gb/s, 4.0 Gb/s and 4.8 Gb/s.

Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents.

Committee(s): JC-16

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