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Title	Document #	Date
RECOMMENDED ESD-CDM TARGET LEVELS	JEP157A	Apr 2022
This document was written with the intent to provide information for quality organizations in both semiconductor companies and their customers to assess and make decisions on safe ESD CDM level requirements. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
STANDARD MANUFACTURERS IDENTIFICATION CODE NOTE: JEP106U was in error starting with bank two an additional continuation code was added, JEP106U should be discarded.	JEP106BE	Jan 2022
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to http://www.jedec.org/Home/MIDCODE_request.cfm Committee(s): JC-42, JC-42.3 Free download. Registration or login required.
Test Procedure for the Measurement of Terrestrial Cosmic Ray Induced Destructive Effects in Power Semiconductor Devices	JEP151A	Jan 2022
This test method defines the requirements and procedures for terrestrial destructive* single-event effects (SEE) for example, single-event breakdown (SEB), single-event latch-up (SEL) and single-event gate rupture (SEGR) testing . It is valid when using an accelerator, generating a nucleon beam of either; 1) Mono-energetic protons or mono-energetic neutrons of at least 150 MeV energy, or 2) Neutrons from a spallation spectrum with maximum energy of at least 150 MeV. This test method does not apply to testing that uses beams with particles heavier than protons. *This test method addresses a separate risk than does JESD89 tests for non-destructive SEE due to cosmic radiation effects on terrestrial applications. Committee(s): JC-14.1 Free download. Registration or login required.
Guidelines for Representing Switching Losses of SIC MOSFETs in Datasheets	JEP187	Dec 2021
This document describes the impact of measurement and/or setup parameters on switching losses of power semiconductor switches; focusing primarily on SiC MOSFET turn-on losses. In terms of turn-off losses, the behavior of SiC MOSFETs is similar to that of existing silicon based power MOSFETs, and as such are adequately represented in typical datasheets. Committee(s): JC-70.2 Free download. Registration or login required.
Guideline to Specify a Transient Off-State Withstand Voltage Robustness Indicator in Datasheets for Lateral GaN Power Conversion Devices, Version 1.0	JEP186	Dec 2021
This guideline describes different techniques for specifying a Transient Off-state Withstand Voltage Robustness Indicator in datasheets for lateral GaN power conversion devices. This guideline does not convey preferences for any of the specification types presented, nor does the guideline address formatting of datasheets. This guideline does not indicate nor require that the datasheet parameters are used in production tests, nor specify how the values were obtained. Committee(s): JC-70.1 Free download. Registration or login required.
COPY-EXACT PROCESS FOR MANUFACTURING	JEP185	Aug 2021
This publication defines the requirements for Copy-Exact Process (CEP) matching, real-time process control, monitoring, and ongoing assessment of the CEP. The critical element requirements for inputs, process controls, procedures, process indicators, human factors, equipment/infrastructure and matching outputs are given. Manufacturers, suppliers and their customers may use these methods to define requirements for process transfer within the constraints of their business agreements. Committee(s): JC-14.3 Free download. Registration or login required.
JC-42.6 MANUFACTURER IDENTIFICATION (ID) CODE FOR LOW POWER MEMORIES	JEP166D	Apr 2021
This document defines the JC-42.6 Manufacturer ID. This document covers Manufacturer ID Codes for the following technologies: LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), LPDDR4 (JESD209-4), Wide-IO (JESD229), and Wide-IO2 (JESD229-2). The purpose of this document is to define the Manufacturer ID for these devices. Item No. 1725.03C. See Annex for additions/changes. To make a request for an ID code: https://www.jedec.org/id-codes-low-power-memories Committee(s): JC-42.6 Free download. Registration or login required.
ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING – REPORTING ESD WITHSTAND LEVELS ON DATASHEETS	JEP178	Apr 2021
This document is intended to guide device manufacturers in developing datasheets and to device customers in understanding datasheet entries. Committee(s): JC-14.3 Free download. Registration or login required.
GUIDELINE FOR EVALUATING BIAS TEMPERATURE INSTABILITY OF SILICON CARBIDE METAL-OXIDE-SEMICONDUCTOR DEVICES FOR POWER ELECTRONIC CONVERSION	JEP184	Mar 2021
The scope of this document covers SiC-based PECS devices having a gate dielectric region biased to turn devices on and off. This typically refers to MOS devices such as MOSFETs and IGBTs. In this document, only NMOS devices are discussed as these are dominant for power device applications; however, the procedures apply to PMOS devices as well. Committee(s): JC-70.2 Free download. Registration or login required.
NEAR-TERM DRAM LEVEL ROWHAMMER MITIGATION	JEP300-1	Mar 2021
RAM process node transistor scaling for power and DRAM capacity has made DRAM cells more sensitive to disturbances or transient faults. This sensitivity becomes much worse if external stresses are applied in a meticulously manipulated sequence, such as Rowhammer. Rowhammer related papers have been written outside of JEDEC, but some assumptions used in those papers didn’t explain the problem very clearly or correctly, so the perception for this matter is not precisely understood within the industry. This publication defines the problem and recommends following mitigations to address such concerns across the DRAM industry or academia. Item 1866.01. Committee(s): JC-42 Free download. Registration or login required.
SYSTEM LEVEL ROWHAMMER MITIGATION	JEP301-1	Mar 2021
A DRAM rowhammer security exploit is a serious threat to cloud service providers, data centers, laptops, smart phones, self-driving cars and IoT devices. Hardware research and development will take time. DRAM components, DRAM DIMMs, System-on-chip (SoC), chipsets and system products have their own design cycle time and overall life time. This publication recommends best practices to mitigate the security risks from rowhammer attacks. Item 1866.02. Committee(s): JC-42 Free download. Registration or login required.
APPLICATION THERMAL DERATING METHODOLOGIES:	JEP149.01	Jan 2021
This publication applies to the application of integrated circuits and their associated packages in end use designs. It summarizes the methodology of thermal derating and the suitability of such methodologies. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
Guidelines for measuring the threshold voltage (VT) of SiC MOSFETs	JEP183	Jan 2021
This publication describes the guidelines for VT measurement methods and conditioning prior to VT testing in SiC power MOSFETs to reduce or eliminate the effect of the aforementioned hysteresis. Committee(s): JC-70.1 Free download. Registration or login required.
GUIDELINE FOR SWITCHING RELIABILITY EVALUATION PROCEDURES FOR GALLIUM NITRIDE POWER CONVERSION DEVICES	JEP180.01	Jan 2021
This document is intended for use by GaN product suppliers and related power electronic industries. It provides guidelines for evaluating the switching reliability of GaN power switches and assuring their reliable use in power conversion applications. It is applicable to planar enhancement-mode, depletion-mode, GaN integrated power solutions and cascode GaN power switches. Committee(s): JC-70.1 Free download. Registration or login required.
TEST METHOD FOR CONTINUOUS-SWITCHING EVALUATION OF GALLIUM NITRIDE POWER CONVERSION DEVICES	JEP182	Jan 2021
This document is intended for use in the GaN power semiconductor and related power electronic industries and provides guidelines for test methods and circuits to be used for continuous-switching tests of GaN power conversion devices. Committee(s): JC-70.1 Free download. Registration or login required.
SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNS This is an editorial revision, details can be found in Annex F.	JEP162A.01	Jan 2021
This document, while establishing the complex nature of System Level ESD, proposes that an efficient ESD design can only be achieved when the interaction of the various components under ESD conditions are analyzed at the system level. This objective requires an appropriate characterization of the components and a methodology to assess the entire system using simulation data. This is applicable to system failures of different categories (such as hard, soft, and electromagnetic interference (EMI)). This type of systematic approach is long overdue and represents an advanced design approach which replaces the misconception, as discussed in detail in JEP161, that a system will be sufficiently robust if all components exceed a certain ESD level. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
REQUIREMENTS FOR MICROELECTRONIC SCREENING AND TEST OPTIMIZATION:	JEP121B	Dec 2020
The purpose of this document provides the basis for the optimization of 100% screening/stress operations and sample inspection test activities. This document is designed to assist the manufacturer in optimizing the test flow while maintaining and/or improving assurance of providing high quality and reliable product in an efficient manner. This will allow for optimization of testing that is not adding value, hence, reducing cycle time and costs. Committee(s): JC-13, JC-13.2 Free download. Registration or login required.
CHARACTERIZATION OF INTERFACIAL ADHESION IN SEMICONDUCTOR PACKAGES	JEP167A	Nov 2020
This document identifies methods used for the characterization of die adhesion. It gives guidance which method to apply in which phase of the product or technology life cycle. Committee(s): JC-14.1 Free download. Registration or login required.
ECXML Guidelines for Electronic Thermal System Level Models – XML Requirements	JEP181	Sep 2020
This standard establishes the requirements for the exchange of electronic thermal system level simulation models between supplier and end user in a single neutral file format. The data is held in an XML format, conforming to an XML schema that this document describes. Committee(s): JC-15 Free download. Registration or login required.
ECXML Guidelines for Electronic Thermal System Level Models – XML Requirements Schema	JEP181_Schema_R1p0	Sep 2020
In conjunction with JEP181, for user support this file is the entire “XML Requirements Schema”. Committee(s): JC-15 Free download. Registration or login required.

Standards & Documents Search

RECOMMENDED ESD-CDM TARGET LEVELS

STANDARD MANUFACTURERS IDENTIFICATION CODE

Test Procedure for the Measurement of Terrestrial Cosmic Ray Induced Destructive Effects in Power Semiconductor Devices

Guidelines for Representing Switching Losses of SIC MOSFETs in Datasheets

Guideline to Specify a Transient Off-State Withstand Voltage Robustness Indicator in Datasheets for Lateral GaN Power Conversion Devices, Version 1.0

COPY-EXACT PROCESS FOR MANUFACTURING

JC-42.6 MANUFACTURER IDENTIFICATION (ID) CODE FOR LOW POWER MEMORIES

ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING – REPORTING ESD WITHSTAND LEVELS ON DATASHEETS

GUIDELINE FOR EVALUATING BIAS TEMPERATURE INSTABILITY OF SILICON CARBIDE METAL-OXIDE-SEMICONDUCTOR DEVICES FOR POWER ELECTRONIC CONVERSION

NEAR-TERM DRAM LEVEL ROWHAMMER MITIGATION

SYSTEM LEVEL ROWHAMMER MITIGATION

APPLICATION THERMAL DERATING METHODOLOGIES:

Guidelines for measuring the threshold voltage (VT) of SiC MOSFETs

GUIDELINE FOR SWITCHING RELIABILITY EVALUATION PROCEDURES FOR GALLIUM NITRIDE POWER CONVERSION DEVICES

TEST METHOD FOR CONTINUOUS-SWITCHING EVALUATION OF GALLIUM NITRIDE POWER CONVERSION DEVICES

SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNS

REQUIREMENTS FOR MICROELECTRONIC SCREENING AND TEST OPTIMIZATION:

CHARACTERIZATION OF INTERFACIAL ADHESION IN SEMICONDUCTOR PACKAGES

ECXML Guidelines for Electronic Thermal System Level Models – XML Requirements

ECXML Guidelines for Electronic Thermal System Level Models – XML Requirements Schema

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