Global Standards for the Microelectronics Industry
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| Title | Document # |
Date |
|---|---|---|
DDR5 UDIMM Raw Card Annex BRelease Number: Version 1.0 |
JESD308-U0-RCB | Jul 2022 |
This annex JESD308-U0-RCB, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Raw Card B Annex defines the design detail of x8, 2 Package Ranks DDR5 UDIMM. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard. Item 2265.11A Committee(s): JC-45.3 Free download. Registration or login required. |
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DDR5 UDIMM Raw Card Annex ERelease Number: Version 1.0 |
JESD308-U4-RCE | Jul 2022 |
This annex JESD308-U4-RCE, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) with 4-bit ECC (EC4 SODIMM) Raw Card E Annex" defines the design detail of x8, 2 Package Ranks DDR5 ECC UDIMM. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard. Item 2265.12A Committee(s): JC-45.3 Free download. Registration or login required. |
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DDR5 UDIMM Raw Card Annex ARelease Number: Version 1.0 |
JESD308-U0-RCA | Jul 2022 |
This annex JESD308-U0-RCA, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Raw Card AAnnex defines the design detail of x8, 1 Package Rank DDR5 UDIMM. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard. Item 2265.13A Committee(s): JC-45.3 Free download. Registration or login required. |
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DDR5 UDIMM Raw Card Annex ARelease Number: Version 1.0 |
JESD308-U0-RCA | Jul 2022 |
This annex JESD308-U0-RCA, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Raw Card AAnnex defines the design detail of x8, 1 Package Rank DDR5 UDIMM. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard. Item 2265.13A Committee(s): JC-45.3 Free download. Registration or login required. |
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DDR5 UDIMM Raw Card Annex DRelease Number: Version 1.0 |
JESD308-U4-RCD | Jul 2022 |
This annex JESD308-U4-RCD, DDR5 Unbuffered Dual Inline Memory Module with 4-bit ECC (EC4UDIMM) Raw Card D Annex defines the design detail of x8, 1 Package Rank DDR5 UDIMM with 4-bit ECC. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard. Item 2265.14A Free download. Registration or login required. |
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DDR5 UDIMM Raw Card Annex CRelease Number: Version 1.0 |
JESD308-U0-RCC | Jul 2022 |
This annex JESD308-U0-RCC, “DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Raw Card C Annex” defines the design detail of x16, 1 Package Ranks DDR5 UDIMM. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard. Item 2265.08A Committee(s): JC-45.3 Free download. Registration or login required. |
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SPD5118 HUB AND SERIAL PRESENCE DETECT DEVICE STANDARDRelease Number: Version 1.5 |
JESD300-5B | Jul 2022 |
This standard defines the specifications of interface parameters, signaling protocols, and features for DDR5 Serial Presence Detect EEPROM with Hub function (SPD5 Hub) and integrated Temperature Sensor (TS) as used for memory module applications. The Hub feature allows isolation of a local bus from a Controller host bus. The designation SPD5118 or generic term SPD5 Hub refers to the devices specified by this standard. Committee Item 600.02A Committee(s): JC-40.1 Free download. Registration or login required. |
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DDR5 Serial Presence Detect (SPD) ContentsRelease Number: Version 1.0 |
JESD400-5 | Jun 2022 |
This document describes the serial presence detect (SPD) values for all DDR5 memory modules. In this context, “modules” applies to memory modules like traditional Dual In-line Memory Modules (DIMMs) or solder-down motherboard applications. The SPD data provides critical information about all modules on the memory channel and is intended to be use by the system's BIOS in order to properly initialize and optimize the system memory channels. Item 2260.01M Committee(s): JC-45 Free download. Registration or login required. |
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SERIAL FLASH DISCOVERABLE PARAMETERS (SFDP)This document replaces JESD216F.01, Editorial changes to this document were approved by the TG, June 2022 |
JESD216F.02 | Jun 2022 |
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. Any company may request a Function Specific ID by making a request to the JEDEC office at juliec@jedec.org. Please include “Function Specific ID Request, JESD216” in the email subject line. Item 1775.73. Editorial changes listed in Annex, from original publication of JESD216F (December 2021). Committee(s): JC-42.4 Free download. Registration or login required. |
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SOLID STATE DRIVE (SSD) REQUIREMENTS AND ENDURANCE TEST METHOD |
JESD218B.02 | Jun 2022 |
Terminology Update, see Annex. This standard defines JEDEC requirements for solid state drives. For each defined class of solid state drive, the standard defines the conditions of use and the corresponding endurance verification requirements. Although endurance is to be rated based upon the standard conditions of use for the class, the standard also sets out requirements for possible additional use conditions as agreed to between manufacturer and purchaser. Revision A includes further information on SSD Capacity. Items 303.19, 303.20, 303.21, 303.22, 303.23, 303.26, 303.27, 303.28, and 303.32 Committee(s): JC-64.8 Available for purchase: $76.00 Add to Cart Paying JEDEC Members may login for free access. |
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