Standards & Documents Search

Displaying 1 - 6 of 6 documents. Show 5 results per page.

Title	Document #	Date
DDR4 NVDIMM-P BUSS PROTOCOL	JESD304-4	Nov 2020
An NVDIMM-P device is defined as a LRDIMM memory module which provides host controller access to DRAM and/or other memory devices such as persistent memory. A transactional protocol is described for NVDIMM-P, which may be used on a DDR interface allowing operation of both standard DRAM modules and NVDIMM-P modules on the same channel. Item 2233.98K. Committee(s): JC-45.6 Free download. Registration or login required.
JEDEC MODULE SIDEBAND BUS (SidebandBus)	JESD403-1	Oct 2020
This standard defines the assumptions for the system management bus for next generation memory solutions; covering the interface protocol, use of hub devices, and voltages appropriate to these usages. Item 2260.37C. Committee(s): JC-45 Free download. Registration or login required.
BYTE ADDRESSABLE ENERGY BACKED INTERFACE	JESD245D	Jul 2020
The purpose of this standard is definition of an energy backed byte addressable function on a nonvolatile dual in-line memory module (NVDIMM). This standard defines the feature set and commands implemented by the energy backed byte addressable function on the NVDIMM. This standard is used in conjunction with JESD248. Item 2233.54F * A minor editorial change has been made to the table under 8.1.3.2, on page 47 on 9/1/2020, from the original posted version 8/18/2020. If you downloaded prior to 9/1/2020, please discard and use the current version. Committee(s): JC-45.6 Free download. Registration or login required.
DDR4 NVDIMM-N DESIGN SPECIFICATION	JESD248A	Mar 2018
This standard defines the electrical and mechanical requirements for 288-pin, 1.2 Volt (VDD), Double Data Rate, Synchronous SDRAM Nonvolatile Dual In-Line Memory Modules with NAND Flash backup (DDR4 NVDIMM-N). A DDR4 NVDIMM-N is a Hybrid Memory Module with a DDR4 DIMM interface consisting of DRAM that is made nonvolatile through the use of NAND Flash. NVDIMM-N modules adhere to the Byte Addressable Energy Backed Interface Standard, JESD245, that provides detailed logical behavior, interface, and register definitions. These DDR4 NVDIMM-N modules are intended for use as main memory or storage when installed in PCs. This standard is used in conjunction with JESD245. Item 2233.27B Committee(s): JC-45.6 Available for purchase: $80.00 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
ADDENDUM No. 1 to JESD209-4, LOW POWER DOUBLE DATA RATE 4X (LPDDR4X)	JESD209-4-1	Jan 2017
This addendum defines LPDDR4X specifications that supersede the LPDDR4 Standard (JESD209-4) to enable low VDDQ operation of LPDDR4X devices to reduce power consumption. Item 1831.55. Committee(s): JC-45.6 Available for purchase: $80.00 Add to Cart Paying JEDEC Members may login for free access.
FBDIMM STANDARD: DDR2 SDRAM FULLY BUFFERED DIMM (FBDIMM) DESIGN STANDARD	JESD205	Mar 2007
This standard defines the electrical and mechanical requirements for 240-pin, PC2-4200/PC2-5300/PC2-6400, 72 bit-wide, Fully Buffered Double Data Rate Synchronous DRAM Dual In-Line Memory Modules (DDR2 SDRAM FB-DIMMs).These SDRAM FB-DIMMs are intended for use as main memory when installed in systems such as servers and workstations. PC2-4200/PC2-5300/PC2-6400 refers to the DIMM naming convention in which PC2-4200/PC2-5300/PC2-6400 indicates a 240-pin DDR2 DIMM running at 266/333/400 MHz DRAM clock speed and offering 4266/5333/6400 MB/s bandwidth. Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-45, JC-45.4 Free download. Registration or login required.