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DDR4 NVDIMM-N Design Standard

 JESD248A.01 Apr 2023

Terminology update.  

This standard defines the electrical and mechanical requirements for 288-pin, 1.2 Volt (VDD), Double Data Rate, Synchronous SDRAM Non-Volatile Dual In-Line Memory Modules with NAND Flash backup (DDR4 NVDIMM-N). A DDR4 NVDIMM-N is a Hybrid Memory Module with a DDR4 DIMM interface consisting of DRAM that is made non-volatile through the use of NAND Flash.

Committee(s): JC-45.6

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Compute Express Link (CXL™) Memory Module Base Standard

 JESD317 Mar 2023

This standard defines the specifications of interface parameters, signaling protocols, environmental requirements, packaging, and other features as reference for specific target implementations of CXL™-attached memory modules.The purpose is to provide certain reference base targets for CXL™-attached memory modules to enable system design simplification, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-45

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DDR5 DIMM Labels

 JESD401-5A Mar 2023

This standard for labels applies to all DDR5 memory modules to fully describe the key attributes of the module. The label can be in the form of a stick-on label, silk screened onto the assembly, or marked using an alternate customer-readable format, Item 2268.02C

Committee(s): JC-45

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Compute Express Link (CXL) Memory Module Label

Release Number: 1.0 		JESD405-1 Feb 2023

The following labels shall be applied to all CXL memory modules to fully describe the key attributes of the module. The label can be in the form of a stick-on label, silk screened onto the assembly, or marked using an alternate customer-readable format.

Committee(s): JC-45

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Annex F, R/C F, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification

Release Number: 33 		MODULE4.20.26.F Feb 2023

This specification defines the electrical and mechanical requirements for Raw Card F, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Item 2231.43.

Committee(s): JC-45.3

JESD21-C Solid State Memory Documents Main Page

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DDR5 Serial Presence Detect (SPD) Contents

Terminology update Release Number: Version 1.1 		JESD400-5A.01 Jan 2023

This standard describes the serial presence detect (SPD) values for all DDR5 memory modules. In this context, “modules” applies to memory modules like traditional Dual In-line Memory Modules (DIMMs) or solder-down motherboard applications. The SPD data provides critical information about all modules on the memory channel and is intended to be used by the system's BIOS in order to properly initialize and optimize the system memory channels.

Committee(s): JC-45

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JEDEC MODULE SIDEBAND BUS (SidebandBus)

 JESD403-1B Aug 2022

This standard defines the assumptions for the system management bus for next generation memory solutions; covering the interface protocol, use of hub devices, and voltages appropriate to these usages. Item 2260.56A.

Committee(s): JC-45

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DDR5 SODIMM Raw Card Annex B. Version 1.0

 JESD309-S0-RCB Aug 2022

This annex JESD309-S0-RCB, DDR5 Small Outline Dual Inline Memory Module with 0-bit ECC (EC0 SODIMM) Raw Card B Annex" defines the design detail of x8, 2 Package Ranks DDR5 NECC SODIMM. The common feature of DDR5 SODIMM such as the connector pinout can be found in the JESD309, DDR5 Small Outline Dual Inline Memory Module (SODIMM) Common Standard.

Committee(s): JC-45.3

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DDR5 UDIMM Raw Card Annex E

Release Number: Version 1.0 		JESD308-U4-RCE Jul 2022

This annex JESD308-U4-RCE, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) with 4-bit ECC (EC4 SODIMM) Raw Card E Annex" defines the design detail of x8, 2 Package Ranks DDR5 ECC UDIMM. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard. Item 2265.12A

Committee(s): JC-45.3

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DDR5 UDIMM Raw Card Annex B

Release Number: Version 1.0 		JESD308-U0-RCB Jul 2022

This annex JESD308-U0-RCB, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Raw Card B Annex defines the design detail of x8, 2 Package Ranks DDR5 UDIMM. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard. Item 2265.11A

Committee(s): JC-45.3

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