Global Standards for the Microelectronics Industry
Standards & Documents Search
| Title | Document # |
Date |
|---|---|---|
SERIAL FLASH DISCOVERABLE PARAMETERS (SFDP)This document replaces JESD216F.01, Editorial changes to this document were approved by the TG, June 2022 |
JESD216F.02 | Jun 2022 |
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. Any company may request a Function Specific ID by making a request to the JEDEC office at juliec@jedec.org. Please include “Function Specific ID Request, JESD216” in the email subject line. Item 1775.73. Editorial changes listed in Annex, from original publication of JESD216F (December 2021). Committee(s): JC-42.4 Free download. Registration or login required. |
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Definition of the EE1002 and EE1002A Serial Presence Detect (SPD) EEPROMs |
SPD4.1.3-01 | May 2022 |
Release No. 19.01. Item 1739.02E, Terminology update. JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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EXPANDED SERIAL PERIPHERAL INTERFACE (xSPI) FOR NONVOLATILE MEMORY DEVICES |
JESD251C | May 2022 |
This standard specifies the eXpanded Serial Peripheral Interface (xSPI) for Non Volatile Memory Devices, which provides high data throughput, low signal count, and limited backward compatibility with legacy Serial Peripheral Interface (SPI) devices. It is primarily for use in computing, automotive, Internet Of Things (IOT), embedded systems and mobile systems, between host processing and peripheral devices. The xSPI electrical interface can deliver up to 400 MBytes per second raw data throughput. Item 1775.74. Committee(s): JC-42.4 Free download. Registration or login required. |
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Mobile Platform Memory Module Thermal Sensor Component Specification |
MODULE4.7 | May 2022 |
Release No. 16.This replaces Release 15 and includes the following editorial changes: 1) Replaced master/slave with controller/target 2) Checked for presence of other sensitive words 3) Added Tables and Figures in Table of Contents(Release 15, Item 1640.07) Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Definitions of the EE1004-v 4 Kbit Serial Presence Detect (SPD) EEPROM and TSE2004av 4 Kbit SPD EEPROM with Temperature Sensor (TS) for Memory Module Applications |
SPD4.1.6-01 | May 2022 |
Release 26.01, Terminology update This standard defines the specifications of interface parameters, signaling protocols, and features for Serial Presence Detect (SPD) EEPROM (EE) and Temperature Sensor (TS) as used for memory module applications. Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Definition of the TSE2002av Serial Presence Detect (SPD) EEPROM with Temperature Sensor (TS) for Memory Module Applications |
SPD4.1.4-01 | May 2022 |
Release No. 21.01, Terminology update.This standard defines the specifications of interface parameters, signaling protocols, and features for Serial Presence Detect (SPD) EEPROMs and Temperature Sensor (TS) as used for memory module applications. The designation TSE2002av refers to the family of devices specified by this document. Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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TEMPERATURE RANGE AND MEASUREMENTS FOR COMPONENTS AND MODULES |
JESD402-1A | Mar 2022 |
This document specifies standard temperature ranges that may be used, by way of referencing JESD402-1, in other standards, specifications, and datasheets when defining temperature related specifications. Items 1855.13, 1855.16, 1855.22, and 1855.24 Committee(s): JC-42 Free download. Registration or login required. |
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High Bandwidth Memory DRAM (HBM3) |
JESD238 | Jan 2022 |
The HBM3 DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM3 DRAM uses a wide-interface architecture to achieve high-speed, low power operation. Each channel interface maintains a 64 bit data bus operating at double data rate (DDR). Item 1837.98. Committee(s): JC-42.2 Free download. Registration or login required. |
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STANDARD MANUFACTURERS IDENTIFICATION CODENOTE: JEP106U was in error starting with bank two an additional continuation code was added, JEP106U should be discarded. |
JEP106BE | Jan 2022 |
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to http://www.jedec.org/Home/MIDCODE_request.cfm Free download. Registration or login required. |
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NAND FLASH INTERFACE INTEROPERABILITY |
JESD230E | Oct 2021 |
This document defines a standard NAND flash device interface interoperability standard that provides means for a system to be designed that can support Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices that are interoperable between JEDEC and ONFI member implementations. This standard was jointly developed by JEDEC and the Open NAND Flash Interface Workgroup, hereafter referred to as ONFI. Item 1767.57 Committee(s): JC-42.4 Free download. Registration or login required. |
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