Global Standards for the Microelectronics Industry
JEDEC DDR5 Workshop: Day 1 Agenda
Tuesday, October 8 • Santa Clara, CA
Tuesday, October 15 • Hsinchu, Taiwan
|8:30-9:30AM||Onsite check-in for registered attendees|
Mian Quddus, JEDEC Chairman
Overview of System/Application Requirements Influencing Definition of DDR5
Presenter: Jonathan Hinkle, Lenovo
The DRAM and main memory of computing systems is one of the most critical components to system performance and since the earliest memory devices, JEDEC has set the standards used by all of the industry. The next definition of DRAM has now emerged in its final form with the release of the DDR5 specification, in response to assessments regarding future system requirements, memory architectural considerations and memory device manufacturing considerations. This presentation will review the key system and memory device requirements that drove the definition of the DDR5 industry standard.
DDR5 Introduction, Overview and DDR4/DDR5 Comparison
Presenter: Chris Cox, Intel
This presentation will review the key aspects of DDR5 – introducing the new technology (architecture, interface, addressing, functions and features, packages, modules). Key differences from DDR4 will be summarized – including implications of BL16, new command structure,1N/2N commands, MPC command, Mode Register changes, mirroring command bus, write pattern mode, pin eliminations, DFE, new refresh modes, etc. This introduction sets the stage for the subsequent detailed presentations that will cover these topics in detail.
DDR5 Power-on, Initialization and Training
Presenter: Chris Cox, Intel
This presentation will cover power on and initialization, enumeration PDN mode, new chip select training mode, command training mode, retraining pattern mode, enhanced write leveling mode, read preamble training, MPC, etc.
DDR5 Write/Read Operations, Refresh
Presenter: Matt Prather, Micron
More details coming soon.
DDR5 Manufacturing and Reliability Features & Utilization
Presenter: Sam Byungsoo Kim, SK Hynix
This presentation will cover connectivity, on-die ECC and its value to the industry, error check scrub (manual and automatic modes) and its related transparency modes, and post-package repair (both soft and hard PPR).
DDR5 Performance-Boost & Power-Saving Features, Modes and Usage Techniques
Presenter: Taek W. Kim, Samsung
What makes DDR5 so different from DDR4? Many of the new features will make DDR5 differentiated from its predecessor, but not as much as its performance-boost and power-savings. DDR5 will come with longer burst length and same bank refresh powered by lower VDD/VPP, and this combination produces substantial improvement such as 2X better effective bandwidth and lower power consumption. This session will identify features that DDR5 adopted to enable those two features to be evolved from DDR4.
Program, topics and speakers subject to change without notice.