Global Standards for the Microelectronics Industry
JC-45 DRAM Modules
The scope of JC-45 is to develop standards for DRAM modules, cards, and socket interfaces. These standards are to address architectural, electrical, test, and SPD issues relating to memory design and manufacturing for commercial applications.
Memory module is defined as a single or multiple PCBs that predominantly include multiple memory, logic, and passive devices in a planar or 3D layout for use with sockets.
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|DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard||JESD308||May 2022|
|DDR5 DIMM Labels||JESD401-5||May 2022|
|DDR5 RDIMM Standard, Annex C||JESD305-R8-RCC||Apr 2022|
|DDR5 RDIMM Standard, Annex F||JESD305-R8-RCF||Apr 2022|
|DDR5 RDIMM Standard Annex E||JESD305-R8-RCE||Apr 2022|
|BYTE ADDRESSABLE ENERGY BACKED INTERFACE||JESD245E||Apr 2022|
|DDR5 RDIMM Standard Annex D||JESD305-R8-RCD||Apr 2022|
|DDR5 RDIMM Standard Annex B||JESD305-R4-RCB||Apr 2022|
|DDR5 RDIMM Standard Annex A||JESD305-R8-RCA||Mar 2022|
|Annex D, Raw Card D, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification||MODULE4.20.25.D||Mar 2022|