JEDEC Committee:
JC-45 DRAM Modules

The scope of JC-45 is to develop standards for DRAM modules, cards, and socket interfaces. These standards are to address architectural, electrical, test, and SPD issues relating to memory design and manufacturing for commercial applications.

Memory module is defined as a single or multiple PCBs that predominantly include multiple memory, logic, and passive devices in a planar or 3D layout for use with sockets.


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Recent Documents

DDR5 Serial Presence Detect (SPD) Contents Version 1.1 JESD400-5A Sep 2022
JEDEC MODULE SIDEBAND BUS (SidebandBus) JESD403-1B Aug 2022
DDR5 SODIMM Raw Card Annex B. Version 1.0 JESD309-S0-RCB Aug 2022
DDR5 UDIMM Raw Card Annex A JESD308-U0-RCA Jul 2022
DDR5 UDIMM Raw Card Annex E JESD308-U4-RCE Jul 2022
DDR5 UDIMM Raw Card Annex B JESD308-U0-RCB Jul 2022
DDR5 UDIMM Raw Card Annex A JESD308-U0-RCA Jul 2022
DDR5 UDIMM Raw Card Annex C JESD308-U0-RCC Jul 2022
DDR5 SODIMM Raw Card Annex E JESDJESD309-S4-RCE Jun 2022
DDR5 SODIMM Raw Card Annex D Version 1.0 JESD309-S4-RCD Jun 2022