Global Standards for the Microelectronics Industry
JEDEC Committee:
JC-42 Solid State Memories
The products within JC-42's scope include all memory integrated circuits and programmable logic devices, whether static or dynamic, without regard to their fabrication technology or application. Examples include large static and dynamic RAMs, ROMs, EEPROMs, and PLDs. Activities include the development of technical information and standards pertaining to pinouts, operational characteristics including reading and writing algorithms, test parameters, characterization, and registration formats. The committee maintains liaisons with other JEDEC committees and outside organizations to promote wide acceptance of the committee’s actions.
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Recent Documents
GRAPHICS DOUBLE DATA RATE (GDDR5X) SGRAM STANDARD | JESD232A.01 | Mar 2023 |
GRAPHICS DOUBLE DATA RATE (GDDR5) SGRAM STANDARD | JESD212C.01 | Jan 2023 |
HIGH BANDWIDTH MEMORY (HBM3) DRAM | JESD238A | Jan 2023 |
Secure Serial Flash Bus Transactions | JESD254 | Dec 2022 |
Serial NOR Security Hardware Abstraction Layer | JESD261 | Nov 2022 |
STANDARD MANUFACTURERS IDENTIFICATION CODE | JEP106BF | Oct 2022 |
DDR5 SDRAM | JESD79-5B | Aug 2022 |
SERIAL FLASH DISCOVERABLE PARAMETERS (SFDP) | JESD216F.02 | Jun 2022 |
Definition of the EE1002 and EE1002A Serial Presence Detect (SPD) EEPROMs | SPD4.1.3-01 | May 2022 |
EXPANDED SERIAL PERIPHERAL INTERFACE (xSPI) FOR NONVOLATILE MEMORY DEVICES | JESD251C | May 2022 |