Global Standards for the Microelectronics Industry
Main Memory: DDR4 & DDR5 SDRAM
Semiconductor memory plays an essential role in the development of countless electronic devices ranging from computers and gaming consoles to televisions and telecommunications products. JEDEC standards encompass virtually every key standard for semiconductor memory in the market today.
JEDEC DDR5
JEDEC published its widely-anticipated JESD79-5 DDR5 SDRAM standard in July 2020, and a second update, JESD79-5B, in August 2022. The standard addresses demand requirements being driven by intensive cloud and enterprise data center applications, providing developers with twice the performance and much improved power efficiency. JESD79-5B DDR5 is available for download from the JEDEC website. Read more about the DDR5 standard here.
JEDEC DDR4
First published in September 2012 and most recently updated in January 2020, the JEDEC DDR4 standard has been defined to provide higher performance, with improved reliability and reduced power, thereby representing a significant achievement relative to previous DRAM memory technologies. DDR4 (JESD79-4C) is available for download from the JEDEC website.
JC-42 Committee
Looking towards the future, JEDEC's JC-42 Committee for Solid State Memories stands at the forefront of the ongoing effort to produce next generation memory device standards. As with all JEDEC standards development activities, industry participation is welcome. Learn more about membership and join today.
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Recent Documents
| DEFINITION OF the SSTUB32865 28-bit 1:2 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS | JESD82-24.01 | Jan 2023 |
| DEFINITION OF THE SSTV32852 2.5 V 24-BIT TO 48-BIT SSTL_2 REGISTERED BUFFER FOR 1U STACKED DDR DIMM APPLICATIONS: | JESD82-6A.01 | Jan 2023 |
| DEFINITION OF THE SSTV16857 2.5 V, 14-BIT SSTL_2 REGISTERED BUFFER FOR DDR DIMM APPLICATIONS: | JESD82-3B.01 | Jan 2023 |
| LRDIMM DDR3 MEMORY BUFFER (MB) | JESD82-30.01 | Jan 2023 |
| DEFINITION OF the SSTUB32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS | JESD82-25.01 | Jan 2023 |
| DDR4 REGISTERING CLOCK DRIVER (DDR4RCD02) | JESD82-31A.01 | Jan 2023 |
| DEFINITION OF THE SSTUB32868 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS | JESD82-26.01 | Jan 2023 |
| DEFINITION OF the SSTUA32S869 AND SSTUA32D869 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS | JESD82-23.01 | Jan 2023 |
| DDR5 Serial Presence Detect (SPD) Contents | JESD400-5A.01 | Jan 2023 |
| FBDIMM: ADVANCED MEMORY BUFFER (AMB) | JESDJESD82-20A.01 | Jan 2023 |
Events and Meetings
| JC-16,40,42,45,63,64 | Seattle | 6 - 9 Mar 2023 |
| JC-16,40,42,45,63,64 | Jeju | 5 - 8 Jun 2023 |
| JC-16,40,42,45,63,64 | Vancouver | 28 - 31 Aug 2023 |
| JC-16,40,42,45,63,64 | Maui | 4 - 7 Dec 2023 |
| JC-16,40,42,45,63,64 | Montreal | 26 - 29 Aug 2024 |
