Main Memory: DDR4 & DDR5 SDRAM

Semiconductor memory plays an essential role in the development of countless electronic devices ranging from computers and gaming consoles to televisions and telecommunications products. JEDEC standards encompass virtually every key standard for semiconductor memory in the market today.


The JEDEC DDR5 standard is currently in development in JEDEC's JC-42 Committee for Solid State Memories. JEDEC DDR5 will offer improved performance with greater power efficiency as compared to previous generation DRAM technologies. As planned, DDR5 will provide double the bandwidth and density over DDR4, along with delivering improved channel efficiency. These enhancements, combined with a more user-friendly interface for server and client platforms, will enable high performance and improved power management in a wide variety of applications.

Contribute to the development of DDR5: Find out more about JEDEC membership and join today!


First published in September 2012 and most recently updated in January 2020, the JEDEC DDR4 standard has been defined to provide higher performance, with improved reliability and reduced power, thereby representing a significant achievement relative to previous DRAM memory technologies. DDR4 (JESD79-4C) is available for download from the JEDEC website. DDR4 offers a range of innovative features designed to enable high speed operation and broad applicability in a variety of applications including servers, laptops, desktop PCs and consumer products. In addition, the new technology has been defined with a goal of simplifying migration and enabling adoption of an industry-wide standard.
The per-pin data rate for DDR4 is specified as 1.6 giga transfers per second to an initial maximum objective of 3.2 giga transfers per second. With DDR3 exceeding its original targeted performance of 1.6 GT/s, it is likely that higher performance speed grades will be added in a future DDR4 update. Other DDR4 attributes tightly intertwined with the planned speed grades, enabling device functionality as well as application adoption, include: a pseudo open drain interface on the DQ bus, a geardown mode for 2,667 MT/s per DQ and beyond, bank group architecture, internally generated VrefDQ and improved training modes. The DDR4 architecture is an 8n prefetch with two or four selectable bank groups. This design will permit the DDR4 memory devices to have separate activation, read, write or refresh operations underway in each unique bank group. This concept will also improve overall memory efficiency and bandwidth, especially when small memory granularities are used. Additional features include:
  • Three data width offerings: x4, x8 and x16
  • New JEDEC POD12 (1.2V) interface standard for DDR4
  • Differential signaling for the clock and strobes
  • Nominal and dynamic ODT: Improvements to the ODT protocol and a new Park Mode allow for a nominal termination and dynamic write termination without having to drive the ODT pin
  • Burst length of 8 and burst chop of 4
  • Data masking
  • DBI: to help reduce power consumption and improve data signal integrity, this feature informs the DRAM as to whether the true or inverted data should be stored
  • 512 K page size for x4 devices: reduces power (less activation power), and extends the usefulness of x4 devices, which allow for more efficient EDC solutions for high-end systems
  • Programmable refresh: Reducing performance penalty of dense DDR4 devices by allowing for refresh intervals ranging from 1x to .0625x the normal refresh interval
  • CRC computation/validation across the data bus: Enabling error detection capability for data transfers – especially beneficial during write operations and in non-ECC memory applications
  • New CA parity for command/address bus: Providing a low-cost method (parity) to verify the integrity of command and address transfers over a link, for all operations
  • Per-DRAM Addressability: Can uniquely select and program DRAMs within a memory structure
  • DLL off mode supported
In addition, DDR4 has been designed in such a way that stacked memory devices may prove to be a key factor during the lifetime of the technology, with stacks of up to 8 memory devices presenting only a single signal load.


The JEDEC DDR3 SDRAM standard describes an evolutionary memory device offering improved performance, lower power and greater functionality than earlier generation memory devices (e.g. DDR1 and DDR2). The JEDEC DDR3 publication defines specification details that enable manufacturers to produce memory devices offering double the performance and density as previous generation (DDR2) devices, with reduced power consumption. The standard is available for download from JEDEC:

JC-42 Committee

Looking towards the future, JEDEC's JC-42 Committee for Solid State Memories stands at the forefront of the ongoing effort to produce next generation memory device standards. As with all JEDEC standards development activities, industry participation is welcome. Learn more about membership and join today.

Search by Keyword or Document Number

Events and Meetings

JC-16,40,42,45,63,64 Maui 7 - 10 Dec 2020
JC-16,40,42,45,63,64 Shanghai 1 - 4 Mar 2021
JC-16,40,42,45,63,64 Seattle 7 - 10 Jun 2021
JC-16,40,42,45,63,64 Denver 30 Aug - 2 Sep 2021
JC-16,40,42,45,63,64 Waikoloa 6 - 9 Dec 2021