Registered Outlines: JEP95

JEP95, JEDEC Registered and Standard Outlines for Solid State and Related Products, is a compilation of some 3000 pages of outline drawings for microelectronic packages including transistors, diodes, DIPS, chip carriers, sockets, and package interface BGA outlines in both inch and metric versions. There are over 500 registrations in all.

The JEDEC JC-11 Committee on Mechanical Standardization develops the outlines in JEP95 and is responsible for updating the publication.

An annual updating service for JEP95 is available by subscription. Subscribers receive periodic electronic updates for replacement or insertion into the hard copy JEP95. Each year approximately 4-6 updates are distributed.

A complete hard copy of JEP95 is available for purchase. The hard copy comes in two 4” wide 3-ring binders so that future updates can be added with ease. A master index is included.

JEDEC Design Guides (was JESD95-1, now section 4 in JEP95)
Carrier Outlines (CO)
Carrier Standards (CS)
Diode Outline (DO)
Microelectronic Outline (MO)
Microelectronic Standards (MS)
Transistor Outline (TO)
Transistor Standards (TS)

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Events and Meetings

JC-16,40,42,45,63,64 Taipei 5 - 8 Mar 2018
JC-16,40,42,45,63,64 Vancouver 4 - 7 Jun 2018
JC-16,40,42,45,63,64 Charlotte 10 - 13 Sep 2018
JC-16, 40, 42, 45, 63, 64 Maui 3 - 6 Dec 2018
JC-16,40,42,45,63,64 Milan 4 - 7 Mar 2019

Related Committees and Subcommittees

JC-11 Mechanical Standardization
JC-11.10 Microelectronic Ceramic Packages
JC-11.11 Microelectronic Plastic Packages
JC-11.14 Microelectronic Assemblies
JC-11.2 Design Requirements
JC-11.4 Uncased Devices
JC-11.7 IEC Interface